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| author | James Molloy <james.molloy@arm.com> | 2014-08-06 10:42:18 +0000 |
|---|---|---|
| committer | James Molloy <james.molloy@arm.com> | 2014-08-06 10:42:18 +0000 |
| commit | f089ab70f4670dff148c210683964556f7e18d4c (patch) | |
| tree | 8700a3a20ff577d2c6209a0f66068132f62b63ea /llvm/lib | |
| parent | bc9f9928b70a20de3f0b5076dd74e9cf33b8e324 (diff) | |
| download | bcm5719-llvm-f089ab70f4670dff148c210683964556f7e18d4c.tar.gz bcm5719-llvm-f089ab70f4670dff148c210683964556f7e18d4c.zip | |
[AArch64] Conditional selects are expensive on out-of-order cores.
Specifically Cortex-A57. This probably applies to Cyclone too but I haven't enabled it for that as I can't test it.
This gives ~4% improvement on SPEC 174.vpr, and ~1% in 471.omnetpp.
llvm-svn: 214957
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 2f55b4a19f9..44d3b34cccc 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -477,6 +477,10 @@ AArch64TargetLowering::AArch64TargetLowering(TargetMachine &TM) setOperationAction(ISD::FROUND, Ty, Legal); } } + + // Prefer likely predicted branches to selects on out-of-order cores. + if (Subtarget->isCortexA57()) + PredictableSelectIsExpensive = true; } void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) { |

