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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-04-22 22:48:38 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-04-22 22:48:38 +0000 |
| commit | efa3fe14d14e427e56a19a11983f8f68246a8c9d (patch) | |
| tree | d421ad3e70f463c5d485eea5078ed7cc46b79fd7 /llvm/lib | |
| parent | 784ec12a3c3d1de370c35ee527f7d5d57b13cd98 (diff) | |
| download | bcm5719-llvm-efa3fe14d14e427e56a19a11983f8f68246a8c9d.tar.gz bcm5719-llvm-efa3fe14d14e427e56a19a11983f8f68246a8c9d.zip | |
AMDGPU: Re-visit nodes in performAndCombine
This fixes test regressions when i64 loads/stores are made promote.
llvm-svn: 267240
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index 92ed678ba8f..4878e5b7a22 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -2229,6 +2229,11 @@ SDValue AMDGPUTargetLowering::performAndCombine(SDNode *N, SDValue LoAnd = DAG.getNode(ISD::AND, SL, MVT::i32, Lo, LoRHS); SDValue HiAnd = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, HiRHS); + // Re-visit the ands. It's possible we eliminated one of them and it could + // simplify the vector. + DCI.AddToWorklist(Lo.getNode()); + DCI.AddToWorklist(Hi.getNode()); + SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, LoAnd, HiAnd); return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec); } |
