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| author | Clement Courbet <courbet@google.com> | 2018-05-02 13:40:48 +0000 |
|---|---|---|
| committer | Clement Courbet <courbet@google.com> | 2018-05-02 13:40:48 +0000 |
| commit | eeb2123a839fe7a6bb25d70f941d50e81ff33cf5 (patch) | |
| tree | b4e0b30488625bd0c6b4d0af63c5f7ba0873e23f /llvm/lib | |
| parent | da54914cde172a8e7a5c27a4be9e5e0772fca6cd (diff) | |
| download | bcm5719-llvm-eeb2123a839fe7a6bb25d70f941d50e81ff33cf5.tar.gz bcm5719-llvm-eeb2123a839fe7a6bb25d70f941d50e81ff33cf5.zip | |
[X86] Fix scheduling info for VMPSADBWYrmi.
https://reviews.llvm.org/D46356
llvm-svn: 331355
Diffstat (limited to 'llvm/lib')
| -rwxr-xr-x | llvm/lib/Target/X86/X86SchedBroadwell.td | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td index 0531ef5700b..19946259715 100755 --- a/llvm/lib/Target/X86/X86SchedBroadwell.td +++ b/llvm/lib/Target/X86/X86SchedBroadwell.td @@ -11,7 +11,6 @@ // scheduling and other instruction cost heuristics. // //===----------------------------------------------------------------------===// - def BroadwellModel : SchedMachineModel { // All x86 instructions are modeled as a single micro-op, and BW can decode 4 // instructions per cycle. @@ -156,9 +155,9 @@ def : WriteRes<WriteFStore, [BWPort237, BWPort4]>; def : WriteRes<WriteFMove, [BWPort5]>; defm : BWWriteResPair<WriteFAdd, [BWPort1], 3, [1], 1, 5>; // Floating point add/sub. -defm : BWWriteResPair<WriteFAddY, [BWPort1], 3, [1], 1, 6>; // Floating point add/sub (YMM/ZMM). +defm : BWWriteResPair<WriteFAddY, [BWPort1], 3, [1], 1, 7>; // Floating point add/sub (YMM/ZMM). defm : BWWriteResPair<WriteFCmp, [BWPort1], 3, [1], 1, 5>; // Floating point compare. -defm : BWWriteResPair<WriteFCmpY, [BWPort1], 3, [1], 1, 6>; // Floating point compare (YMM/ZMM). +defm : BWWriteResPair<WriteFCmpY, [BWPort1], 3, [1], 1, 7>; // Floating point compare (YMM/ZMM). defm : BWWriteResPair<WriteFCom, [BWPort1], 3>; // Floating point compare to flags. defm : BWWriteResPair<WriteFMul, [BWPort0], 5, [1], 1, 5>; // Floating point multiplication. defm : BWWriteResPair<WriteFMulY, [BWPort0], 5, [1], 1, 7>; // Floating point multiplication (YMM/ZMM). @@ -1369,8 +1368,20 @@ def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> { } def: InstRW<[BWWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m", "ILD_F(16|32|64)m", + "VADDPDYrm", + "VADDPSYrm", + "VADDSUBPDYrm", + "VADDSUBPSYrm", + "VCMPPDYrmi", + "VCMPPSYrmi", "VCVTPS2DQYrm", - "VCVTTPS2DQYrm")>; + "VCVTTPS2DQYrm", + "VMAX(C?)PDYrm", + "VMAX(C?)PSYrm", + "VMIN(C?)PDYrm", + "VMIN(C?)PSYrm", + "VSUBPDYrm", + "VSUBPSYrm")>; def BWWriteResGroup102 : SchedWriteRes<[BWPort5,BWPort23]> { let Latency = 9; @@ -1643,7 +1654,7 @@ def: InstRW<[BWWriteResGroup137_1], (instregex "(V?)SQRTSSr")>; def BWWriteResGroup138 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> { let Latency = 13; let NumMicroOps = 4; - let ResourceCycles = [1,2,1,7]; + let ResourceCycles = [1,2,1]; } def: InstRW<[BWWriteResGroup138], (instregex "VMPSADBWYrmi")>; |
