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authorTom Stellard <thomas.stellard@amd.com>2015-08-29 01:58:21 +0000
committerTom Stellard <thomas.stellard@amd.com>2015-08-29 01:58:21 +0000
commiteea72ccbf2d8379a04b7783bc6a72a69ad5dface (patch)
treede1a1677c16ed72c704482112d5c65ba3cb996c8 /llvm/lib
parentb8ce14c4c3bc634e9610ddda8970b1208d2c5526 (diff)
downloadbcm5719-llvm-eea72ccbf2d8379a04b7783bc6a72a69ad5dface.tar.gz
bcm5719-llvm-eea72ccbf2d8379a04b7783bc6a72a69ad5dface.zip
AMDGPU/SI: Fix some invaild assumptions when folding 64-bit immediates
Summary: We were assuming tha if the use operand had a sub-register that the immediate was 64-bits, but this was breaking the case of folding a 64-bit immediate into another 64-bit instruction. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D12255 llvm-svn: 246354
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/AMDGPU/SIFoldOperands.cpp6
1 files changed, 5 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index 5609f3ce2f2..eff9c072f40 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -211,8 +211,12 @@ static void foldOperand(MachineOperand &OpToFold, MachineInstr *UseMI,
Imm = APInt(64, OpToFold.getImm());
+ const MCInstrDesc &FoldDesc = TII->get(OpToFold.getParent()->getOpcode());
+ const TargetRegisterClass *FoldRC =
+ TRI.getRegClass(FoldDesc.OpInfo[0].RegClass);
+
// Split 64-bit constants into 32-bits for folding.
- if (UseOp.getSubReg()) {
+ if (FoldRC->getSize() == 8 && UseOp.getSubReg()) {
if (UseRC->getSize() != 8)
return;
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