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| author | Craig Topper <craig.topper@gmail.com> | 2017-02-26 06:45:35 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2017-02-26 06:45:35 +0000 |
| commit | ed64904c7439b85f350dd24786e21c0005c232b4 (patch) | |
| tree | 3e8a9cc650ee25025984f0aa735f8e71f0e9c51f /llvm/lib | |
| parent | a87b40051d2fe31335993a47a110c64528df06d7 (diff) | |
| download | bcm5719-llvm-ed64904c7439b85f350dd24786e21c0005c232b4.tar.gz bcm5719-llvm-ed64904c7439b85f350dd24786e21c0005c232b4.zip | |
[X86] Fix the execution domain for scalar SQRT intrinsic instruction.
llvm-svn: 296284
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index 9764b05a859..0c169798289 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -3333,7 +3333,7 @@ multiclass sse_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC, Sched<[itins.Sched.Folded, ReadAfterLd]>, Requires<[target, OptForSize]>; - let isCodeGenOnly = 1, Constraints = "$src1 = $dst" in { + let isCodeGenOnly = 1, Constraints = "$src1 = $dst", ExeDomain = d in { def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), []>, Sched<[itins.Sched.Folded, ReadAfterLd]>; @@ -3377,7 +3377,7 @@ multiclass avx_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC, def m : I<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), [], itins.rm, d>, Sched<[itins.Sched.Folded, ReadAfterLd]>; - let isCodeGenOnly = 1 in { + let isCodeGenOnly = 1, ExeDomain = d in { def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), |
