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| author | Sander de Smalen <sander.desmalen@arm.com> | 2018-07-17 08:52:45 +0000 |
|---|---|---|
| committer | Sander de Smalen <sander.desmalen@arm.com> | 2018-07-17 08:52:45 +0000 |
| commit | ec229abb9b01cedd4c7706e5829a3bf875537bef (patch) | |
| tree | 02ccd3d59425408f5f76dc391c915ce709b8dec4 /llvm/lib | |
| parent | ff71afe8099c1c3e3e3b6a5048ff104053c4a208 (diff) | |
| download | bcm5719-llvm-ec229abb9b01cedd4c7706e5829a3bf875537bef.tar.gz bcm5719-llvm-ec229abb9b01cedd4c7706e5829a3bf875537bef.zip | |
[AArch64][SVE] Asm: Support for SPLICE instruction.
The SPLICE instruction splices two vectors into one vector using a
predicate. It copies the active elements from the first vector, and
then fills the remaining elements with the low-numbered elements from
the second vector.
The instruction has the following form, e.g.
splice z0.b, p0, z0.b, z1.b
for 8-bit elements. It also supports 16, 32 and
64-bit elements.
llvm-svn: 337253
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/SVEInstrFormats.td | 25 |
2 files changed, 26 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index c3885c6d7e9..1edc36944a1 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -112,6 +112,7 @@ let Predicates = [HasSVE] in { // Select elements from either vector (predicated) defm SEL_ZPZZ : sve_int_sel_vvv<"sel">; + defm SPLICE_ZPZ : sve_int_perm_splice<"splice">; defm COMPACT_ZPZ : sve_int_perm_compact<"compact">; defm INSR_ZR : sve_int_perm_insrs<"insr">; defm INSR_ZV : sve_int_perm_insrv<"insr">; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index 0d5b8b13b8e..2c37be691bb 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -2610,6 +2610,31 @@ multiclass sve_int_perm_last_v<bit ab, string asm> { def _D : sve_int_perm_last_v<0b11, ab, asm, ZPR64, FPR64>; } +class sve_int_perm_splice<bits<2> sz8_64, string asm, ZPRRegOp zprty> +: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm), + asm, "\t$Zdn, $Pg, $_Zdn, $Zm", + "", + []>, Sched<[]> { + bits<3> Pg; + bits<5> Zdn; + bits<5> Zm; + let Inst{31-24} = 0b00000101; + let Inst{23-22} = sz8_64; + let Inst{21-13} = 0b101100100; + let Inst{12-10} = Pg; + let Inst{9-5} = Zm; + let Inst{4-0} = Zdn; + + let Constraints = "$Zdn = $_Zdn"; +} + +multiclass sve_int_perm_splice<string asm> { + def _B : sve_int_perm_splice<0b00, asm, ZPR8>; + def _H : sve_int_perm_splice<0b01, asm, ZPR16>; + def _S : sve_int_perm_splice<0b10, asm, ZPR32>; + def _D : sve_int_perm_splice<0b11, asm, ZPR64>; +} + class sve_int_perm_cpy_r<bits<2> sz8_64, string asm, ZPRRegOp zprty, RegisterClass srcRegType> : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, srcRegType:$Rn), |
