summaryrefslogtreecommitdiffstats
path: root/llvm/lib
diff options
context:
space:
mode:
authorSander de Smalen <sander.desmalen@arm.com>2018-07-11 11:22:26 +0000
committerSander de Smalen <sander.desmalen@arm.com>2018-07-11 11:22:26 +0000
commitea45a89e5c4472f492da059782500551649e32c6 (patch)
treea7e7efb14a9711e9b928670479b541ab2bae4bbc /llvm/lib
parentf51c853cf167046be0b658bc179e86df7ce22ee3 (diff)
downloadbcm5719-llvm-ea45a89e5c4472f492da059782500551649e32c6.tar.gz
bcm5719-llvm-ea45a89e5c4472f492da059782500551649e32c6.zip
[AArch64][SVE] Asm: Support for COMPACT instruction.
The compact instruction shuffles active elements of vector into lowest numbered elements and sets remaining elements to zero. e.g. compact z0.s, p0, z1.s llvm-svn: 336789
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td2
-rw-r--r--llvm/lib/Target/AArch64/SVEInstrFormats.td22
2 files changed, 24 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index d747d76fab5..dc28f14a59d 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -112,6 +112,8 @@ let Predicates = [HasSVE] in {
// Select elements from either vector (predicated)
defm SEL_ZPZZ : sve_int_sel_vvv<"sel">;
+ defm COMPACT_ZPZ : sve_int_perm_compact<"compact">;
+
def AND_PPzPP : sve_int_pred_log<0b0000, "and">;
def BIC_PPzPP : sve_int_pred_log<0b0001, "bic">;
def EOR_PPzPP : sve_int_pred_log<0b0010, "eor">;
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index b8e67f6ab04..de9cb79d246 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -2574,6 +2574,28 @@ multiclass sve_int_perm_cpy_v<string asm> {
(!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPR3bAny:$Pg, FPR64:$Vn), 1>;
}
+class sve_int_perm_compact<bit sz, string asm, ZPRRegOp zprty>
+: I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn),
+ asm, "\t$Zd, $Pg, $Zn",
+ "",
+ []>, Sched<[]> {
+ bits<3> Pg;
+ bits<5> Zd;
+ bits<5> Zn;
+ let Inst{31-23} = 0b000001011;
+ let Inst{22} = sz;
+ let Inst{21-13} = 0b100001100;
+ let Inst{12-10} = Pg;
+ let Inst{9-5} = Zn;
+ let Inst{4-0} = Zd;
+}
+
+multiclass sve_int_perm_compact<string asm> {
+ def _S : sve_int_perm_compact<0b0, asm, ZPR32>;
+ def _D : sve_int_perm_compact<0b1, asm, ZPR64>;
+}
+
+
//===----------------------------------------------------------------------===//
// SVE Memory - Contiguous Load Group
//===----------------------------------------------------------------------===//
OpenPOWER on IntegriCloud