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| author | Matheus Almeida <matheus.almeida@imgtec.com> | 2014-03-26 16:09:43 +0000 |
|---|---|---|
| committer | Matheus Almeida <matheus.almeida@imgtec.com> | 2014-03-26 16:09:43 +0000 |
| commit | ea06727f03593389529c6bf22781bb5f0a31906e (patch) | |
| tree | 811654f1ddc5643a2ab4ce405db7e38ce2658839 /llvm/lib | |
| parent | c511f43b675a3eb877d552bb0b0b8100ee2465fd (diff) | |
| download | bcm5719-llvm-ea06727f03593389529c6bf22781bb5f0a31906e.tar.gz bcm5719-llvm-ea06727f03593389529c6bf22781bb5f0a31906e.zip | |
[mips] Use TwoOperandAliasConstraint for ArithLogicR instructions.
This enables TableGen to generate an additional two operand matcher
for our ArithLogicR class of instructions (constituted by 3 register operands).
E.g.: and $1, $2 <=> and $1, $1, $2
llvm-svn: 204826
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Mips/Mips64InstrInfo.td | 24 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.td | 1 |
2 files changed, 1 insertions, 24 deletions
diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td index 43ffee2c9ff..e44a52e517f 100644 --- a/llvm/lib/Target/Mips/Mips64InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td @@ -363,36 +363,12 @@ def : InstAlias<"daddu $rs, $imm", def : InstAlias<"dadd $rs, $imm", (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm), 0>; -def : InstAlias<"dadd $rs, $rt", - (DADD GPR64Opnd:$rs, GPR64Opnd:$rs, GPR64Opnd:$rt), - 0>; -def : InstAlias<"daddu $rs, $rt", - (DADDu GPR64Opnd:$rs, GPR64Opnd:$rs, GPR64Opnd:$rt), - 0>; -def : InstAlias<"dsub $rs, $rt", - (DSUB GPR64Opnd:$rs, GPR64Opnd:$rs, GPR64Opnd:$rt), - 0>; -def : InstAlias<"dsubu $rs, $rt", - (DSUBu GPR64Opnd:$rs, GPR64Opnd:$rs, GPR64Opnd:$rt), - 0>; def : InstAlias<"add $rs, $imm", (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>; def : InstAlias<"addu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>; -def : InstAlias<"add $rs, $rt", - (ADD GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), - 0>; -def : InstAlias<"addu $rs, $rt", - (ADDu GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), - 0>; -def : InstAlias<"sub $rs, $rt", - (SUB GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), - 0>; -def : InstAlias<"subu $rs, $rt", - (SUBu GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), - 0>; let isPseudo=1, usesCustomInserter=1, isCodeGenOnly=1 in { def SUBi : MipsInst<(outs GPR32Opnd: $rt), (ins GPR32Opnd: $rs, simm16: $imm), "sub\t$rt, $rs, $imm", [], II_DSUB, Pseudo>; diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index ed0b69eb094..1584d296709 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -426,6 +426,7 @@ class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0, [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> { let isCommutable = isComm; let isReMaterializable = 1; + let TwoOperandAliasConstraint = "$rd = $rs"; } // Arithmetic and logical instructions with 2 register operands. |
