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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-03-27 18:38:51 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-03-27 18:38:51 +0000 |
| commit | e9f36790310a7b5a05dc134ece554fd75e2d98a9 (patch) | |
| tree | fb2184ca296c13f451eb2ae3b5f1ddca2746050c /llvm/lib | |
| parent | 01c33b818950af40a7bd2089211a24db8c1f7dd0 (diff) | |
| download | bcm5719-llvm-e9f36790310a7b5a05dc134ece554fd75e2d98a9.tar.gz bcm5719-llvm-e9f36790310a7b5a05dc134ece554fd75e2d98a9.zip | |
AMDGPU: Fix FP restore from being reordered with stack ops
In a function, s5 is used as the frame base SGPR. If a function
is calling another function, during the call sequence
it is copied to a preserved SGPR and restored.
Before it was possible for the scheduler to move stack operations
before the restore of s5, since there's nothing to associate
a frame index access with the restore.
Add an implicit use of s5 to the adjcallstack pseudo which ends
the call sequence to preven this from happening. I'm not 100%
satisfied with this solution, but I'm not sure what else would be
better.
llvm-svn: 328650
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 6a46dfdb225..58afd167e0c 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -3351,8 +3351,13 @@ MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter( case AMDGPU::ADJCALLSTACKDOWN: { const SIMachineFunctionInfo *Info = MF->getInfo<SIMachineFunctionInfo>(); MachineInstrBuilder MIB(*MF, &MI); + + // Add an implicit use of the frame offset reg to prevent the restore copy + // inserted after the call from being reorderd after stack operations in the + // the caller's frame. MIB.addReg(Info->getStackPtrOffsetReg(), RegState::ImplicitDefine) - .addReg(Info->getStackPtrOffsetReg(), RegState::Implicit); + .addReg(Info->getStackPtrOffsetReg(), RegState::Implicit) + .addReg(Info->getFrameOffsetReg(), RegState::Implicit); return BB; } case AMDGPU::SI_CALL_ISEL: |
