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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-11-03 22:39:52 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-11-03 22:39:52 +0000 |
| commit | e8ed13d94664101410817f4eb09d23b9099f7621 (patch) | |
| tree | ccaf4f1ef48fecf45e552758bd5ca2f2404b5918 /llvm/lib | |
| parent | 192b282bf3dd285da991a6aeb49831d3fd93b85c (diff) | |
| download | bcm5719-llvm-e8ed13d94664101410817f4eb09d23b9099f7621.tar.gz bcm5719-llvm-e8ed13d94664101410817f4eb09d23b9099f7621.zip | |
AMDGPU: s[102:103] is unavailable on VI
llvm-svn: 252000
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 1315b6a7b3a..429bb2fbd87 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -45,9 +45,18 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const { // will physically contain VCC. reserveRegisterTuples(Reserved, AMDGPU::SGPR102_SGPR103); + const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>(); + + if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) { + // SI/CI have 104 SGPRs. VI has 102. We need to shift down the reservation + // for VCC/FLAT_SCR. + reserveRegisterTuples(Reserved, AMDGPU::SGPR98_SGPR99); + reserveRegisterTuples(Reserved, AMDGPU::SGPR100_SGPR101); + } + // Tonga and Iceland can only allocate a fixed number of SGPRs due // to a hw bug. - if (MF.getSubtarget<AMDGPUSubtarget>().hasSGPRInitBug()) { + if (ST.hasSGPRInitBug()) { unsigned NumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs(); // Reserve some SGPRs for FLAT_SCRATCH and VCC (4 SGPRs). // Assume XNACK_MASK is unused. |
