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| author | Jan Vesely <jan.vesely@rutgers.edu> | 2016-11-15 23:55:15 +0000 |
|---|---|---|
| committer | Jan Vesely <jan.vesely@rutgers.edu> | 2016-11-15 23:55:15 +0000 |
| commit | e8cc395e4f643a78f6a6122a9c13c6869091dc88 (patch) | |
| tree | a534a6558b32552fba89d0aedeec61df4f106f73 /llvm/lib | |
| parent | e6f6d4c2f28de0f06452434dc0be25994d3a709f (diff) | |
| download | bcm5719-llvm-e8cc395e4f643a78f6a6122a9c13c6869091dc88.tar.gz bcm5719-llvm-e8cc395e4f643a78f6a6122a9c13c6869091dc88.zip | |
AMDGPU/GCN: Exit early in hazard recognizer if there is no vreg argument
wbinvl.* are vector instruction that do not sue vector registers.
v2: check only M?BUF instructions
Differential Revision: https://reviews.llvm.org/D26633
llvm-svn: 287056
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp index 70b7b6b2671..88536289119 100644 --- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp +++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp @@ -400,6 +400,10 @@ int GCNHazardRecognizer::createsVALUHazard(const MachineInstr &MI) { VDataRCID = Desc.OpInfo[VDataIdx].RegClass; if (TII->isMUBUF(MI) || TII->isMTBUF(MI)) { + // There is no hazard if the instruction does not use vector regs + // (like wbinvl1) + if (VDataIdx == -1) + return -1; // For MUBUF/MTBUF instructions this hazard only exists if the // instruction is not using a register in the soffset field. const MachineOperand *SOffset = |
