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authorAmaury de la Vieuville <amaury.dlv@gmail.com>2013-06-14 11:21:35 +0000
committerAmaury de la Vieuville <amaury.dlv@gmail.com>2013-06-14 11:21:35 +0000
commite804ae1188c82ed629391087a32adaccade4da36 (patch)
tree795981a461686567b3a77b76e83740a67a3445fe /llvm/lib
parent0d7012debb41b2d68a784eab05e52a559bc8cba3 (diff)
downloadbcm5719-llvm-e804ae1188c82ed629391087a32adaccade4da36.tar.gz
bcm5719-llvm-e804ae1188c82ed629391087a32adaccade4da36.zip
ARM: fix thumb coprocessor instruction with pre-writeback disassembly
was stc2 p0, c0, [r0]! instead of stc2 p0, c0, [r0,#0]! llvm-svn: 183975
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/ARM/ARMInstrThumb2.td2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td
index ff21bf70ecd..8b114a83264 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -3632,7 +3632,7 @@ multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm> {
let DecoderMethod = "DecodeCopMemInstruction";
}
def _PRE : T2CI<op31_28,
- (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
+ (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
asm, "\t$cop, $CRd, $addr!"> {
bits<13> addr;
bits<4> cop;
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