diff options
author | Duncan Sands <baldrick@free.fr> | 2007-11-09 08:57:19 +0000 |
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committer | Duncan Sands <baldrick@free.fr> | 2007-11-09 08:57:19 +0000 |
commit | e7a9ac929f32a9ec74a09a64daea107ea4ee116e (patch) | |
tree | e9b97a2d4c09c29fed14377afc5236111fd8df7c /llvm/lib | |
parent | bab9dc9433dd78bfb91398093abd58dff50cfd9b (diff) | |
download | bcm5719-llvm-e7a9ac929f32a9ec74a09a64daea107ea4ee116e.tar.gz bcm5719-llvm-e7a9ac929f32a9ec74a09a64daea107ea4ee116e.zip |
Fix some load/store logic that would be wrong for
apints on big-endian machines if the bitwidth is
not a multiple of 8. Introduce a new helper,
MVT::getStoreSizeInBits, and use it.
llvm-svn: 43934
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 12 | ||||
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeDAGTypes.cpp | 4 |
2 files changed, 10 insertions, 6 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 73d7db413f1..7a6e55e9849 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -1713,8 +1713,9 @@ SDOperand DAGCombiner::visitAND(SDNode *N) { // For big endian targets, we need to add an offset to the pointer to // load the correct bytes. For little endian systems, we merely need to // read fewer bytes from the same pointer. - unsigned PtrOff = - (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8; + unsigned LVTStoreBytes = MVT::getStoreSizeInBits(LoadedVT)/8; + unsigned EVTStoreBytes = MVT::getStoreSizeInBits(EVT)/8; + unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; unsigned Alignment = LN0->getAlignment(); SDOperand NewPtr = LN0->getBasePtr(); if (!TLI.isLittleEndian()) { @@ -2991,8 +2992,11 @@ SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { MVT::ValueType PtrType = N0.getOperand(1).getValueType(); // For big endian targets, we need to adjust the offset to the pointer to // load the correct bytes. - if (!TLI.isLittleEndian()) - ShAmt = MVT::getSizeInBits(N0.getValueType()) - ShAmt - EVTBits; + if (!TLI.isLittleEndian()) { + unsigned LVTStoreBits = MVT::getStoreSizeInBits(N0.getValueType()); + unsigned EVTStoreBits = MVT::getStoreSizeInBits(EVT); + ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; + } uint64_t PtrOff = ShAmt / 8; unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAGTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAGTypes.cpp index 11431ee0861..825134130c3 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAGTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAGTypes.cpp @@ -1036,7 +1036,7 @@ void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N, // Big-endian - high bits are at low addresses. Favor aligned loads at // the cost of some bit-fiddling. MVT::ValueType EVT = N->getLoadedVT(); - unsigned EBytes = (MVT::getSizeInBits(EVT) + 7)/8; + unsigned EBytes = MVT::getStoreSizeInBits(EVT)/8; unsigned IncrementSize = MVT::getSizeInBits(NVT)/8; unsigned ExcessBits = (EBytes - IncrementSize)*8; @@ -2069,7 +2069,7 @@ SDOperand DAGTypeLegalizer::ExpandOperand_STORE(StoreSDNode *N, unsigned OpNo) { GetExpandedOp(N->getValue(), Lo, Hi); MVT::ValueType EVT = N->getStoredVT(); - unsigned EBytes = (MVT::getSizeInBits(EVT) + 7)/8; + unsigned EBytes = MVT::getStoreSizeInBits(EVT)/8; unsigned IncrementSize = MVT::getSizeInBits(NVT)/8; unsigned ExcessBits = (EBytes - IncrementSize)*8; MVT::ValueType HiVT = |