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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-01-07 12:38:35 -0500 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2020-01-09 10:29:32 -0500 |
| commit | e71af775684a83f0d1d05ab5225d36830d5aa87e (patch) | |
| tree | 92be526ab7ae8ff9c936bb20f27563dd029c40b8 /llvm/lib | |
| parent | 79450a4ea26a0e9731eaf2629f6dd8c1ffd8f407 (diff) | |
| download | bcm5719-llvm-e71af775684a83f0d1d05ab5225d36830d5aa87e.tar.gz bcm5719-llvm-e71af775684a83f0d1d05ab5225d36830d5aa87e.zip | |
AMDGPU/GlobalISel: Add IMMPopCount xform
Partially fixes BFE pattern import.
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUGISel.td | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h | 3 |
3 files changed, 12 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td index 9b62e54da2b..f9983693a99 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td @@ -214,3 +214,6 @@ def gi_NegateImm : GICustomOperandRenderer<"renderNegateImm">, def gi_bitcast_fpimm_to_i32 : GICustomOperandRenderer<"renderBitcastImm">, GISDNodeXFormEquiv<bitcast_fpimm_to_i32>; + +def gi_IMMPopCount : GICustomOperandRenderer<"renderPopcntImm">, + GISDNodeXFormEquiv<IMMPopCount>; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index c0830ac2a0b..095c667e143 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -2128,6 +2128,12 @@ void AMDGPUInstructionSelector::renderBitcastImm(MachineInstrBuilder &MIB, } } +void AMDGPUInstructionSelector::renderPopcntImm(MachineInstrBuilder &MIB, + const MachineInstr &MI) const { + assert(MI.getOpcode() == TargetOpcode::G_CONSTANT && "Expected G_CONSTANT"); + MIB.addImm(MI.getOperand(1).getCImm()->getValue().countPopulation()); +} + bool AMDGPUInstructionSelector::isInlineImmediate16(int64_t Imm) const { return AMDGPU::isInlinableLiteral16(Imm, STI.hasInv2PiInlineImm()); } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h index c249c7e44e6..0799ace0867 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h @@ -177,6 +177,9 @@ private: void renderBitcastImm(MachineInstrBuilder &MIB, const MachineInstr &MI) const; + void renderPopcntImm(MachineInstrBuilder &MIB, + const MachineInstr &MI) const; + bool isInlineImmediate16(int64_t Imm) const; bool isInlineImmediate32(int64_t Imm) const; bool isInlineImmediate64(int64_t Imm) const; |
