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authorJim Grosbach <grosbach@apple.com>2010-12-10 21:05:07 +0000
committerJim Grosbach <grosbach@apple.com>2010-12-10 21:05:07 +0000
commite69f72493517b940c6c40824ca8356c208bba15a (patch)
treeadb8a5378446ebc112f0c5bfc1d8d18418c93d61 /llvm/lib
parente991a6ee5ad4056e9912ebc3861c3d3320093898 (diff)
downloadbcm5719-llvm-e69f72493517b940c6c40824ca8356c208bba15a.tar.gz
bcm5719-llvm-e69f72493517b940c6c40824ca8356c208bba15a.zip
Fix encoding of 'U' bit for Thumb2 STRD/LDRD instructions. rdar://8755726
llvm-svn: 121524
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp8
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
index bf869f703bc..df28a992913 100644
--- a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
@@ -552,9 +552,9 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
uint32_t ARMMCCodeEmitter::
getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const {
- // {17-13} = reg
- // {12} = (U)nsigned (add == '1', sub == '0')
- // {11-0} = imm8
+ // {12-9} = reg
+ // {8} = (U)nsigned (add == '1', sub == '0')
+ // {7-0} = imm8
unsigned Reg, Imm8;
bool isAdd = true;
// If The first operand isn't a register, we have a label reference.
@@ -576,7 +576,7 @@ getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
uint32_t Binary = (Imm8 >> 2) & 0xff;
// Immediate is always encoded as positive. The 'U' bit controls add vs sub.
if (isAdd)
- Binary |= (1 << 9);
+ Binary |= (1 << 8);
Binary |= (Reg << 9);
return Binary;
}
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