Revert "[ARM] Recommit the glueless lowering of addc/adde in Thumb1, including the amended (no UB anymore) fix for adding/subtracting -2147483648."

Fails check-llvm with ubsan

This reverts commit r298417.

llvm-svn: 298482

3 files changed, 31 insertions, 167 deletions

diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 4f5711ca9a7..72868828596 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -2028,16 +2028,6 @@ static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
   {ARM::RSBSrsi, ARM::RSBrsi},
   {ARM::RSBSrsr, ARM::RSBrsr},
 
-  {ARM::tADDSi3, ARM::tADDi3},
-  {ARM::tADDSi8, ARM::tADDi8},
-  {ARM::tADDSrr, ARM::tADDrr},
-  {ARM::tADCS, ARM::tADC},
-
-  {ARM::tSUBSi3, ARM::tSUBi3},
-  {ARM::tSUBSi8, ARM::tSUBi8},
-  {ARM::tSUBSrr, ARM::tSUBrr},
-  {ARM::tSBCS, ARM::tSBC},
-
   {ARM::t2ADDSri, ARM::t2ADDri},
   {ARM::t2ADDSrr, ARM::t2ADDrr},
   {ARM::t2ADDSrs, ARM::t2ADDrs},
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 24ddb306c66..e3723788223 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -822,10 +822,13 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::SRL,       MVT::i64, Custom);
   setOperationAction(ISD::SRA,       MVT::i64, Custom);
 
-  setOperationAction(ISD::ADDC,      MVT::i32, Custom);
-  setOperationAction(ISD::ADDE,      MVT::i32, Custom);
-  setOperationAction(ISD::SUBC,      MVT::i32, Custom);
-  setOperationAction(ISD::SUBE,      MVT::i32, Custom);
+  if (!Subtarget->isThumb1Only()) {
+    // FIXME: We should do this for Thumb1 as well.
+    setOperationAction(ISD::ADDC,    MVT::i32, Custom);
+    setOperationAction(ISD::ADDE,    MVT::i32, Custom);
+    setOperationAction(ISD::SUBC,    MVT::i32, Custom);
+    setOperationAction(ISD::SUBE,    MVT::i32, Custom);
+  }
 
   if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops())
     setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
@@ -9093,45 +9096,19 @@ void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
 
   // Rename pseudo opcodes.
   unsigned NewOpc = convertAddSubFlagsOpcode(MI.getOpcode());
-  unsigned ccOutIdx;
   if (NewOpc) {
     const ARMBaseInstrInfo *TII = Subtarget->getInstrInfo();
     MCID = &TII->get(NewOpc);
 
-    assert(MCID->getNumOperands() ==
-           MI.getDesc().getNumOperands() + 5 - MI.getDesc().getSize()
-        && "converted opcode should be the same except for cc_out"
-           " (and, on Thumb1, pred)");
+    assert(MCID->getNumOperands() == MI.getDesc().getNumOperands() + 1 &&
+           "converted opcode should be the same except for cc_out");
 
     MI.setDesc(*MCID);
 
     // Add the optional cc_out operand
     MI.addOperand(MachineOperand::CreateReg(0, /*isDef=*/true));
-
-    // On Thumb1, move all input operands to the end, then add the predicate
-    if (Subtarget->isThumb1Only()) {
-      for (unsigned c = MCID->getNumOperands() - 4; c--;) {
-        MI.addOperand(MI.getOperand(1));
-        MI.RemoveOperand(1);
-      }
-
-      // Restore the ties
-      for (unsigned i = MI.getNumOperands(); i--;) {
-        const MachineOperand& op = MI.getOperand(i);
-        if (op.isReg() && op.isUse()) {
-          int DefIdx = MCID->getOperandConstraint(i, MCOI::TIED_TO);
-          if (DefIdx != -1)
-            MI.tieOperands(DefIdx, i);
-        }
-      }
-
-      MI.addOperand(MachineOperand::CreateImm(ARMCC::AL));
-      MI.addOperand(MachineOperand::CreateReg(0, /*isDef=*/false));
-      ccOutIdx = 1;
-    } else
-      ccOutIdx = MCID->getNumOperands() - 1;
-  } else
-    ccOutIdx = MCID->getNumOperands() - 1;
+  }
+  unsigned ccOutIdx = MCID->getNumOperands() - 1;
 
   // Any ARM instruction that sets the 's' bit should specify an optional
   // "cc_out" operand in the last operand position.
@@ -9162,9 +9139,7 @@ void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
   if (deadCPSR) {
     assert(!MI.getOperand(ccOutIdx).getReg() &&
            "expect uninitialized optional cc_out operand");
-    // Thumb1 instructions must have the S bit even if the CPSR is dead.
-    if (!Subtarget->isThumb1Only())
-      return;
+    return;
   }
 
   // If this instruction was defined with an optional CPSR def and its dag node
@@ -9784,48 +9759,6 @@ static SDValue PerformUMLALCombine(SDNode *N, SelectionDAG &DAG,
     return SDValue();
 }
 
-static SDValue PerformAddcSubcCombine(SDNode *N, SelectionDAG &DAG,
-                                      const ARMSubtarget *Subtarget) {
-  if (Subtarget->isThumb1Only()) {
-    SDValue RHS = N->getOperand(1);
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
-      int32_t imm = C->getSExtValue();
-      if (imm < 0 && imm > -2147483648) {
-        SDLoc DL(N);
-        RHS = DAG.getConstant(-imm, DL, MVT::i32);
-        unsigned Opcode = (N->getOpcode() == ARMISD::ADDC) ? ARMISD::SUBC
-                                                           : ARMISD::ADDC;
-        return DAG.getNode(Opcode, DL, N->getVTList(), N->getOperand(0), RHS);
-      }
-    }
-  }
-  return SDValue();
-}
-
-static SDValue PerformAddeSubeCombine(SDNode *N, SelectionDAG &DAG,
-                                      const ARMSubtarget *Subtarget) {
-  if (Subtarget->isThumb1Only()) {
-    SDValue RHS = N->getOperand(1);
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
-      int64_t imm = C->getSExtValue();
-      if (imm < 0) {
-        SDLoc DL(N);
-
-        // The with-carry-in form matches bitwise not instead of the negation.
-        // Effectively, the inverse interpretation of the carry flag already
-        // accounts for part of the negation.
-        RHS = DAG.getConstant(~imm, DL, MVT::i32);
-
-        unsigned Opcode = (N->getOpcode() == ARMISD::ADDE) ? ARMISD::SUBE
-                                                           : ARMISD::ADDE;
-        return DAG.getNode(Opcode, DL, N->getVTList(),
-                           N->getOperand(0), RHS, N->getOperand(2));
-      }
-    }
-  }
-  return SDValue();
-}
-
 /// PerformADDECombine - Target-specific dag combine transform from
 /// ARMISD::ADDC, ARMISD::ADDE, and ISD::MUL_LOHI to MLAL or
 /// ARMISD::ADDC, ARMISD::ADDE and ARMISD::UMLAL to ARMISD::UMAAL
@@ -9834,7 +9767,7 @@ static SDValue PerformADDECombine(SDNode *N,
                                   const ARMSubtarget *Subtarget) {
   // Only ARM and Thumb2 support UMLAL/SMLAL.
   if (Subtarget->isThumb1Only())
-    return PerformAddeSubeCombine(N, DCI.DAG, Subtarget);
+    return SDValue();
 
   // Only perform the checks after legalize when the pattern is available.
   if (DCI.isBeforeLegalize()) return SDValue();
@@ -11934,9 +11867,6 @@ SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
   case ISD::OR:         return PerformORCombine(N, DCI, Subtarget);
   case ISD::XOR:        return PerformXORCombine(N, DCI, Subtarget);
   case ISD::AND:        return PerformANDCombine(N, DCI, Subtarget);
-  case ARMISD::ADDC:
-  case ARMISD::SUBC:    return PerformAddcSubcCombine(N, DCI.DAG, Subtarget);
-  case ARMISD::SUBE:    return PerformAddeSubeCombine(N, DCI.DAG, Subtarget);
   case ARMISD::BFI:     return PerformBFICombine(N, DCI);
   case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI, Subtarget);
   case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td
index c372bcdc262..e6934cb04ef 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb.td
@@ -922,7 +922,7 @@ let isAdd = 1 in {
   def tADC :                      // A8.6.2
     T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
                   "adc", "\t$Rdn, $Rm",
-                  []>, Sched<[WriteALU]>;
+                  [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
 
   // Add immediate
   def tADDi3 :                    // A8.6.4 T1
@@ -950,43 +950,6 @@ let isAdd = 1 in {
                   "add", "\t$Rd, $Rn, $Rm",
                   [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
 
-  /// Similar to the above except these set the 's' bit so the
-  /// instruction modifies the CPSR register.
-  ///
-  /// These opcodes will be converted to the real non-S opcodes by
-  /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
-  let hasPostISelHook = 1, Defs = [CPSR] in {
-    let isCommutable = 1 in
-    def tADCS : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
-                            2, IIC_iALUr,
-                            [(set tGPR:$Rdn, CPSR, (ARMadde tGPR:$Rn, tGPR:$Rm,
-                                                            CPSR))]>,
-                Requires<[IsThumb1Only]>,
-                Sched<[WriteALU]>;
-
-    def tADDSi3 : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
-                              2, IIC_iALUi,
-                              [(set tGPR:$Rd, CPSR, (ARMaddc tGPR:$Rm,
-                                                             imm0_7:$imm3))]>,
-                  Requires<[IsThumb1Only]>,
-                  Sched<[WriteALU]>;
-
-    def tADDSi8 : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, imm0_255:$imm8),
-                              2, IIC_iALUi,
-                              [(set tGPR:$Rdn, CPSR, (ARMaddc tGPR:$Rn,
-                                                      imm8_255:$imm8))]>,
-                  Requires<[IsThumb1Only]>,
-                  Sched<[WriteALU]>;
-
-    let isCommutable = 1 in
-    def tADDSrr : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
-                              2, IIC_iALUr,
-                              [(set tGPR:$Rd, CPSR, (ARMaddc tGPR:$Rn,
-                                                             tGPR:$Rm))]>,
-                  Requires<[IsThumb1Only]>,
-                  Sched<[WriteALU]>;
-  }
-
   let hasSideEffects = 0 in
   def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
                        "add", "\t$Rdn, $Rm", []>,
@@ -1252,7 +1215,7 @@ def tSBC :                      // A8.6.151
   T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
                 IIC_iALUr,
                 "sbc", "\t$Rdn, $Rm",
-                []>,
+                [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>,
                 Sched<[WriteALU]>;
 
 // Subtract immediate
@@ -1289,41 +1252,6 @@ def tSUBrr :                    // A8.6.212
                 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>,
                 Sched<[WriteALU]>;
 
-/// Similar to the above except these set the 's' bit so the
-/// instruction modifies the CPSR register.
-///
-/// These opcodes will be converted to the real non-S opcodes by
-/// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
-let hasPostISelHook = 1, Defs = [CPSR] in {
-  def tSBCS : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
-                          2, IIC_iALUr,
-                          [(set tGPR:$Rdn, CPSR, (ARMsube tGPR:$Rn, tGPR:$Rm,
-                                                          CPSR))]>,
-              Requires<[IsThumb1Only]>,
-              Sched<[WriteALU]>;
-
-  def tSUBSi3 : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
-                            2, IIC_iALUi,
-                            [(set tGPR:$Rd, CPSR, (ARMsubc tGPR:$Rm,
-                                                           imm0_7:$imm3))]>,
-                Requires<[IsThumb1Only]>,
-                Sched<[WriteALU]>;
-
-  def tSUBSi8 : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, imm0_255:$imm8),
-                            2, IIC_iALUi,
-                            [(set tGPR:$Rdn, CPSR, (ARMsubc tGPR:$Rn,
-                                                            imm8_255:$imm8))]>,
-                Requires<[IsThumb1Only]>,
-                Sched<[WriteALU]>;
-
-  def tSUBSrr : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
-                            2, IIC_iALUr,
-                            [(set tGPR:$Rd, CPSR, (ARMsubc tGPR:$Rn,
-                                                           tGPR:$Rm))]>,
-                Requires<[IsThumb1Only]>,
-                Sched<[WriteALU]>;
-}
-
 // Sign-extend byte
 def tSXTB :                     // A8.6.222
   T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
@@ -1484,6 +1412,22 @@ def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
             (tCMPr   tGPR:$Rn, tGPR:$Rm)>;
 
+// Add with carry
+def : T1Pat<(addc   tGPR:$lhs, imm0_7:$rhs),
+            (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
+def : T1Pat<(addc   tGPR:$lhs, imm8_255:$rhs),
+            (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
+def : T1Pat<(addc   tGPR:$lhs, tGPR:$rhs),
+            (tADDrr tGPR:$lhs, tGPR:$rhs)>;
+
+// Subtract with carry
+def : T1Pat<(addc   tGPR:$lhs, imm0_7_neg:$rhs),
+            (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
+def : T1Pat<(addc   tGPR:$lhs, imm8_255_neg:$rhs),
+            (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
+def : T1Pat<(subc   tGPR:$lhs, tGPR:$rhs),
+            (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
+
 // Bswap 16 with load/store
 def : T1Pat<(srl (bswap (extloadi16 t_addrmode_is2:$addr)), (i32 16)),
             (tREV16 (tLDRHi t_addrmode_is2:$addr))>;