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| author | Andrew Trick <atrick@apple.com> | 2012-03-16 05:04:25 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-03-16 05:04:25 +0000 |
| commit | e6913c7245c55fe94c865e912303c3b765c0ab64 (patch) | |
| tree | 0a665e7caa16f9a4b473ef164df1dc8e96506c4c /llvm/lib | |
| parent | c0d0d35117382e33bc8d92f33ad10fe27fba47c5 (diff) | |
| download | bcm5719-llvm-e6913c7245c55fe94c865e912303c3b765c0ab64.tar.gz bcm5719-llvm-e6913c7245c55fe94c865e912303c3b765c0ab64.zip | |
misched: add DAG edges from vreg defs to ExitSU.
These edges are not really necessary, but it is consistent with the
way we currently create physreg edges. Scheduler heuristics that
expect a DAG edge to the block terminator could benefit from this
change. Although in the future I hope we have a better mechanism for
modeling latency across scheduling regions.
llvm-svn: 152895
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/ScheduleDAGInstrs.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp index 54828e28d1d..1c455b95ab0 100644 --- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -201,8 +201,10 @@ void ScheduleDAGInstrs::addSchedBarrierDeps() { if (TRI->isPhysicalRegister(Reg)) Uses[Reg].push_back(&ExitSU); - else + else { assert(!IsPostRA && "Virtual register encountered after regalloc."); + addVRegUseDeps(&ExitSU, i); + } } } else { // For others, e.g. fallthrough, conditional branch, assume the exit |
