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authorArnold Schwaighofer <aschwaighofer@apple.com>2013-02-19 15:27:05 +0000
committerArnold Schwaighofer <aschwaighofer@apple.com>2013-02-19 15:27:05 +0000
commite5083442b26266eeaf2b3675d12e3d78336ad4ae (patch)
tree773e55cb5c2439cdba632c8190ee9960bd3c4d2b /llvm/lib
parentd4409e2cecc376b7226e125fa2bbf9005649e2e3 (diff)
downloadbcm5719-llvm-e5083442b26266eeaf2b3675d12e3d78336ad4ae.tar.gz
bcm5719-llvm-e5083442b26266eeaf2b3675d12e3d78336ad4ae.zip
ARM NEON: Merge a f32 bitcast of a v2i32 extractelt
A vectorized sitfp on doubles will get scalarized to a sequence of an extract_element of <2 x i32>, a bitcast to f32 and a sitofp. Due to the the extract_element, and the bitcast we will uneccessarily generate moves between scalar and vector registers. The patch fixes this by using a COPY_TO_REGCLASS and a EXTRACT_SUBREG to extract the element from the vector instead. radar://13191881 llvm-svn: 175520
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/ARM/ARMInstrNEON.td6
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td
index 901ff64a863..9f68c220777 100644
--- a/llvm/lib/Target/ARM/ARMInstrNEON.td
+++ b/llvm/lib/Target/ARM/ARMInstrNEON.td
@@ -5745,6 +5745,12 @@ def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
+// Fold extracting an element out of a v2i32 into a vfp register.
+def : Pat<(f32 (bitconvert (i32 (extractelt (v2i32 DPR:$src), imm:$lane)))),
+ (f32 (EXTRACT_SUBREG
+ (v2f32 (COPY_TO_REGCLASS (v2i32 DPR:$src), DPR)),
+ (SSubReg_f32_reg imm:$lane)))>;
+
// Vector lengthening move with load, matching extending loads.
// extload, zextload and sextload for a standard lengthening load. Example:
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