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author | Chris Lattner <sabre@nondot.org> | 2007-02-01 01:21:12 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2007-02-01 01:21:12 +0000 |
commit | e3eeb24a86df6a70e3b5d277fa6ababdc3d8be6e (patch) | |
tree | ee1484860a6b67148d58f570206aca6bd5f47b14 /llvm/lib | |
parent | ea0568392e2a5f57693b8bc960d4151b948dea9b (diff) | |
download | bcm5719-llvm-e3eeb24a86df6a70e3b5d277fa6ababdc3d8be6e.tar.gz bcm5719-llvm-e3eeb24a86df6a70e3b5d277fa6ababdc3d8be6e.zip |
Emit a better assertion message for PR1133
llvm-svn: 33736
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 33 |
1 files changed, 18 insertions, 15 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 7e2a2777dfe..af63d369919 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -2663,23 +2663,26 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) { unsigned NumOps = cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); - assert((NumOps & 7) == 2 /*REGDEF*/ && - "Skipped past definitions?"); + if ((NumOps & 7) == 2 /*REGDEF*/) { + // Add NumOps>>3 registers to MatchedRegs. + RegsForValue MatchedRegs; + MatchedRegs.ValueVT = InOperandVal.getValueType(); + MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType(); + for (unsigned i = 0, e = NumOps>>3; i != e; ++i) { + unsigned Reg = + cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg(); + MatchedRegs.Regs.push_back(Reg); + } - // Add NumOps>>3 registers to MatchedRegs. - RegsForValue MatchedRegs; - MatchedRegs.ValueVT = InOperandVal.getValueType(); - MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType(); - for (unsigned i = 0, e = NumOps>>3; i != e; ++i) { - unsigned Reg=cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg(); - MatchedRegs.Regs.push_back(Reg); + // Use the produced MatchedRegs object to + MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, + TLI.getPointerTy()); + MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands); + break; + } else { + assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!"); + assert(0 && "matching constraints for memory operands unimp"); } - - // Use the produced MatchedRegs object to - MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, - TLI.getPointerTy()); - MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands); - break; } TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass; |