diff options
| author | Simon Dardis <simon.dardis@mips.com> | 2018-04-27 15:49:49 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@mips.com> | 2018-04-27 15:49:49 +0000 |
| commit | e3c3c5a7a72ad9afac80fdf0ee34aa1a76ddd5a2 (patch) | |
| tree | f72e9833220c2c152cf25a71d875397e400a0c69 /llvm/lib | |
| parent | 776cd7ad44881d78e7f674aec092107dbfc1f56d (diff) | |
| download | bcm5719-llvm-e3c3c5a7a72ad9afac80fdf0ee34aa1a76ddd5a2.tar.gz bcm5719-llvm-e3c3c5a7a72ad9afac80fdf0ee34aa1a76ddd5a2.zip | |
[mips] Analyze and provide selection patterns microMIPSR6 branches
These branches were previously unanalyzable and unselectable. Add them and
recognize how to generate their inverses.
Reviewers: smaksimovic, atanasyan, abeserminji
Differential Revision: https://reviews.llvm.org/D46113
llvm-svn: 331050
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td | 34 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsSEInstrInfo.cpp | 16 |
2 files changed, 49 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td index 1b6ee463d6b..613ee373b86 100644 --- a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -1725,3 +1725,37 @@ def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), (TAILCALL_MMR6 texternalsym:$dst)>, ISA_MICROMIPS32R6; + +def : MipsPat<(brcond (i32 (setne GPR32:$lhs, 0)), bb:$dst), + (BNEZC_MMR6 GPR32:$lhs, bb:$dst)>, ISA_MICROMIPS32R6; +def : MipsPat<(brcond (i32 (seteq GPR32:$lhs, 0)), bb:$dst), + (BEQZC_MMR6 GPR32:$lhs, bb:$dst)>, ISA_MICROMIPS32R6; + +def : MipsPat<(brcond (i32 (setge GPR32:$lhs, GPR32:$rhs)), bb:$dst), + (BEQZC_MMR6 (SLT_MM GPR32:$lhs, GPR32:$rhs), bb:$dst)>, + ISA_MICROMIPS32R6; +def : MipsPat<(brcond (i32 (setuge GPR32:$lhs, GPR32:$rhs)), bb:$dst), + (BEQZC_MMR6 (SLTu_MM GPR32:$lhs, GPR32:$rhs), bb:$dst)>, + ISA_MICROMIPS32R6; +def : MipsPat<(brcond (i32 (setge GPR32:$lhs, immSExt16:$rhs)), bb:$dst), + (BEQZC_MMR6 (SLTi_MM GPR32:$lhs, immSExt16:$rhs), bb:$dst)>, + ISA_MICROMIPS32R6; +def : MipsPat<(brcond (i32 (setuge GPR32:$lhs, immSExt16:$rhs)), bb:$dst), + (BEQZC_MMR6 (SLTiu_MM GPR32:$lhs, immSExt16:$rhs), bb:$dst)>, + ISA_MICROMIPS32R6; +def : MipsPat<(brcond (i32 (setgt GPR32:$lhs, immSExt16Plus1:$rhs)), bb:$dst), + (BEQZC_MMR6 (SLTi_MM GPR32:$lhs, (Plus1 imm:$rhs)), bb:$dst)>, + ISA_MICROMIPS32R6; +def : MipsPat<(brcond (i32 (setugt GPR32:$lhs, immSExt16Plus1:$rhs)), bb:$dst), + (BEQZC_MMR6 (SLTiu_MM GPR32:$lhs, (Plus1 imm:$rhs)), bb:$dst)>, + ISA_MICROMIPS32R6; + +def : MipsPat<(brcond (i32 (setle GPR32:$lhs, GPR32:$rhs)), bb:$dst), + (BEQZC_MMR6 (SLT_MM GPR32:$rhs, GPR32:$lhs), bb:$dst)>, + ISA_MICROMIPS32R6; +def : MipsPat<(brcond (i32 (setule GPR32:$lhs, GPR32:$rhs)), bb:$dst), + (BEQZC_MMR6 (SLTu_MM GPR32:$rhs, GPR32:$lhs), bb:$dst)>, + ISA_MICROMIPS32R6; + +def : MipsPat<(brcond GPR32:$cond, bb:$dst), + (BNEZC_MMR6 GPR32:$cond, bb:$dst)>, ISA_MICROMIPS32R6; diff --git a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp index e9c08b9465a..6b7156d089f 100644 --- a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp +++ b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp @@ -445,6 +445,14 @@ unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const { case Mips::BGEZC: return Mips::BLTZC; case Mips::BLTZC: return Mips::BGEZC; case Mips::BLEZC: return Mips::BGTZC; + case Mips::BEQZC_MMR6: return Mips::BNEZC_MMR6; + case Mips::BNEZC_MMR6: return Mips::BEQZC_MMR6; + case Mips::BEQC_MMR6: return Mips::BNEC_MMR6; + case Mips::BNEC_MMR6: return Mips::BEQC_MMR6; + case Mips::BGTZC_MMR6: return Mips::BLEZC_MMR6; + case Mips::BGEZC_MMR6: return Mips::BLTZC_MMR6; + case Mips::BLTZC_MMR6: return Mips::BGEZC_MMR6; + case Mips::BLEZC_MMR6: return Mips::BGTZC_MMR6; case Mips::BEQZC64: return Mips::BNEZC64; case Mips::BNEZC64: return Mips::BEQZC64; case Mips::BEQC64: return Mips::BNEC64; @@ -553,7 +561,13 @@ unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const { Opc == Mips::BGTZC64 || Opc == Mips::BGEZC64 || Opc == Mips::BLTZC64 || Opc == Mips::BLEZC64 || Opc == Mips::BC || Opc == Mips::BBIT0 || Opc == Mips::BBIT1 || Opc == Mips::BBIT032 || - Opc == Mips::BBIT132) ? Opc : 0; + Opc == Mips::BBIT132 || Opc == Mips::BC_MMR6 || + Opc == Mips::BEQC_MMR6 || Opc == Mips::BNEC_MMR6 || + Opc == Mips::BLTC_MMR6 || Opc == Mips::BGEC_MMR6 || + Opc == Mips::BLTUC_MMR6 || Opc == Mips::BGEUC_MMR6 || + Opc == Mips::BGTZC_MMR6 || Opc == Mips::BLEZC_MMR6 || + Opc == Mips::BGEZC_MMR6 || Opc == Mips::BLTZC_MMR6 || + Opc == Mips::BEQZC_MMR6 || Opc == Mips::BNEZC_MMR6) ? Opc : 0; } void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB, |
