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| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-11-10 16:59:55 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-11-10 16:59:55 +0000 |
| commit | e373163e951f4c8a4d44e4aae8edbaff8f7bdf14 (patch) | |
| tree | 53aef58d0bd25af6495f9786aa8a38bc61e612ae /llvm/lib | |
| parent | 3d3de4e6c3c30e22047552654fd83f8a25682a4a (diff) | |
| download | bcm5719-llvm-e373163e951f4c8a4d44e4aae8edbaff8f7bdf14.tar.gz bcm5719-llvm-e373163e951f4c8a4d44e4aae8edbaff8f7bdf14.zip | |
fix a bunch of regressions
llvm-svn: 24269
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaISelPattern.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp index 96684baaf8d..eb13486c7f2 100644 --- a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp @@ -1295,11 +1295,11 @@ unsigned AlphaISel::SelectExpr(SDOperand N) { if (SrcType == MVT::f32) { Tmp2 = MakeReg(MVT::f64); - BuildMI(BB, Alpha::CVTST, 1, Tmp2).addReg(Alpha::F31).addReg(Tmp1); + BuildMI(BB, Alpha::CVTST, 1, Tmp2).addReg(Tmp1); Tmp1 = Tmp2; } Tmp2 = MakeReg(MVT::f64); - BuildMI(BB, Alpha::CVTTQ, 1, Tmp2).addReg(Alpha::F31).addReg(Tmp1); + BuildMI(BB, Alpha::CVTTQ, 1, Tmp2).addReg(Tmp1); MoveFP2Int(Tmp2, Result, true); return Result; |
