Convert the last getPhysicalRegisterRegClass in VirtRegRewriter.cpp to

getMinimalPhysRegClass. It was used to produce spills, and it is better to
use the most specific class if possible.

Update getLoadStoreRegOpcode to handle GR32_AD.

llvm-svn: 108115

2 files changed, 3 insertions, 2 deletions

diff --git a/llvm/lib/CodeGen/VirtRegRewriter.cpp b/llvm/lib/CodeGen/VirtRegRewriter.cpp
index 9895f09d9b1..57a1500e6e9 100644
--- a/llvm/lib/CodeGen/VirtRegRewriter.cpp
+++ b/llvm/lib/CodeGen/VirtRegRewriter.cpp
@@ -1703,7 +1703,7 @@ bool LocalRewriter::InsertEmergencySpills(MachineInstr *MI) {
   std::vector<unsigned> &EmSpills = VRM->getEmergencySpills(MI);
   for (unsigned i = 0, e = EmSpills.size(); i != e; ++i) {
     unsigned PhysReg = EmSpills[i];
-    const TargetRegisterClass *RC = TRI->getPhysicalRegisterRegClass(PhysReg);
+    const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysReg);
     assert(RC && "Unable to determine register class!");
     int SS = VRM->getEmergencySpillSlot(RC);
     if (UsedSS.count(SS))
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 55adc263dd5..439f8d259c8 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -1960,7 +1960,8 @@ static unsigned getLoadStoreRegOpcode(unsigned Reg,
                                       bool load) {
   if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
     return load ? X86::MOV64rm : X86::MOV64mr;
-  } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
+  } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass ||
+             RC == &X86::GR32_ADRegClass) {
     return load ? X86::MOV32rm : X86::MOV32mr;
   } else if (RC == &X86::GR16RegClass) {
     return load ? X86::MOV16rm : X86::MOV16mr;