[X86] Put some cases in switch statements back on one line to be more compact and make it easier to see the similarities. NFC

It looks like someone ran clang-format over this entire file which reformatted these switches into a multiline form. But I think the single line form is more useful here.

llvm-svn: 336077

1 files changed, 186 insertions, 566 deletions

diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp
index ae4b1e79c54..9ca5de6c30b 100644
--- a/llvm/lib/Target/X86/X86MCInstLower.cpp
+++ b/llvm/lib/Target/X86/X86MCInstLower.cpp
@@ -455,47 +455,20 @@ ReSimplify:
         X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) {
       unsigned NewOpc;
       switch (OutMI.getOpcode()) {
-      default:
-        llvm_unreachable("Invalid opcode");
-      case X86::VMOVZPQILo2PQIrr:
-        NewOpc = X86::VMOVPQI2QIrr;
-        break;
-      case X86::VMOVAPDrr:
-        NewOpc = X86::VMOVAPDrr_REV;
-        break;
-      case X86::VMOVAPDYrr:
-        NewOpc = X86::VMOVAPDYrr_REV;
-        break;
-      case X86::VMOVAPSrr:
-        NewOpc = X86::VMOVAPSrr_REV;
-        break;
-      case X86::VMOVAPSYrr:
-        NewOpc = X86::VMOVAPSYrr_REV;
-        break;
-      case X86::VMOVDQArr:
-        NewOpc = X86::VMOVDQArr_REV;
-        break;
-      case X86::VMOVDQAYrr:
-        NewOpc = X86::VMOVDQAYrr_REV;
-        break;
-      case X86::VMOVDQUrr:
-        NewOpc = X86::VMOVDQUrr_REV;
-        break;
-      case X86::VMOVDQUYrr:
-        NewOpc = X86::VMOVDQUYrr_REV;
-        break;
-      case X86::VMOVUPDrr:
-        NewOpc = X86::VMOVUPDrr_REV;
-        break;
-      case X86::VMOVUPDYrr:
-        NewOpc = X86::VMOVUPDYrr_REV;
-        break;
-      case X86::VMOVUPSrr:
-        NewOpc = X86::VMOVUPSrr_REV;
-        break;
-      case X86::VMOVUPSYrr:
-        NewOpc = X86::VMOVUPSYrr_REV;
-        break;
+      default: llvm_unreachable("Invalid opcode");
+      case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr;   break;
+      case X86::VMOVAPDrr:        NewOpc = X86::VMOVAPDrr_REV;  break;
+      case X86::VMOVAPDYrr:       NewOpc = X86::VMOVAPDYrr_REV; break;
+      case X86::VMOVAPSrr:        NewOpc = X86::VMOVAPSrr_REV;  break;
+      case X86::VMOVAPSYrr:       NewOpc = X86::VMOVAPSYrr_REV; break;
+      case X86::VMOVDQArr:        NewOpc = X86::VMOVDQArr_REV;  break;
+      case X86::VMOVDQAYrr:       NewOpc = X86::VMOVDQAYrr_REV; break;
+      case X86::VMOVDQUrr:        NewOpc = X86::VMOVDQUrr_REV;  break;
+      case X86::VMOVDQUYrr:       NewOpc = X86::VMOVDQUYrr_REV; break;
+      case X86::VMOVUPDrr:        NewOpc = X86::VMOVUPDrr_REV;  break;
+      case X86::VMOVUPDYrr:       NewOpc = X86::VMOVUPDYrr_REV; break;
+      case X86::VMOVUPSrr:        NewOpc = X86::VMOVUPSrr_REV;  break;
+      case X86::VMOVUPSYrr:       NewOpc = X86::VMOVUPSYrr_REV; break;
       }
       OutMI.setOpcode(NewOpc);
     }
@@ -507,14 +480,9 @@ ReSimplify:
         X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {
       unsigned NewOpc;
       switch (OutMI.getOpcode()) {
-      default:
-        llvm_unreachable("Invalid opcode");
-      case X86::VMOVSDrr:
-        NewOpc = X86::VMOVSDrr_REV;
-        break;
-      case X86::VMOVSSrr:
-        NewOpc = X86::VMOVSSrr_REV;
-        break;
+      default: llvm_unreachable("Invalid opcode");
+      case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
+      case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
       }
       OutMI.setOpcode(NewOpc);
     }
@@ -593,20 +561,11 @@ ReSimplify:
     if (!AsmPrinter.getSubtarget().is64Bit()) {
       unsigned Opcode;
       switch (OutMI.getOpcode()) {
-      default:
-        llvm_unreachable("Invalid opcode");
-      case X86::DEC16r:
-        Opcode = X86::DEC16r_alt;
-        break;
-      case X86::DEC32r:
-        Opcode = X86::DEC32r_alt;
-        break;
-      case X86::INC16r:
-        Opcode = X86::INC16r_alt;
-        break;
-      case X86::INC32r:
-        Opcode = X86::INC32r_alt;
-        break;
+      default: llvm_unreachable("Invalid opcode");
+      case X86::DEC16r: Opcode = X86::DEC16r_alt; break;
+      case X86::DEC32r: Opcode = X86::DEC32r_alt; break;
+      case X86::INC16r: Opcode = X86::INC16r_alt; break;
+      case X86::INC32r: Opcode = X86::INC32r_alt; break;
       }
       OutMI.setOpcode(Opcode);
     }
@@ -615,169 +574,63 @@ ReSimplify:
   // These are pseudo-ops for OR to help with the OR->ADD transformation.  We do
   // this with an ugly goto in case the resultant OR uses EAX and needs the
   // short form.
-  case X86::ADD16rr_DB:
-    OutMI.setOpcode(X86::OR16rr);
-    goto ReSimplify;
-  case X86::ADD32rr_DB:
-    OutMI.setOpcode(X86::OR32rr);
-    goto ReSimplify;
-  case X86::ADD64rr_DB:
-    OutMI.setOpcode(X86::OR64rr);
-    goto ReSimplify;
-  case X86::ADD16ri_DB:
-    OutMI.setOpcode(X86::OR16ri);
-    goto ReSimplify;
-  case X86::ADD32ri_DB:
-    OutMI.setOpcode(X86::OR32ri);
-    goto ReSimplify;
-  case X86::ADD64ri32_DB:
-    OutMI.setOpcode(X86::OR64ri32);
-    goto ReSimplify;
-  case X86::ADD16ri8_DB:
-    OutMI.setOpcode(X86::OR16ri8);
-    goto ReSimplify;
-  case X86::ADD32ri8_DB:
-    OutMI.setOpcode(X86::OR32ri8);
-    goto ReSimplify;
-  case X86::ADD64ri8_DB:
-    OutMI.setOpcode(X86::OR64ri8);
-    goto ReSimplify;
+  case X86::ADD16rr_DB:   OutMI.setOpcode(X86::OR16rr);   goto ReSimplify;
+  case X86::ADD32rr_DB:   OutMI.setOpcode(X86::OR32rr);   goto ReSimplify;
+  case X86::ADD64rr_DB:   OutMI.setOpcode(X86::OR64rr);   goto ReSimplify;
+  case X86::ADD16ri_DB:   OutMI.setOpcode(X86::OR16ri);   goto ReSimplify;
+  case X86::ADD32ri_DB:   OutMI.setOpcode(X86::OR32ri);   goto ReSimplify;
+  case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
+  case X86::ADD16ri8_DB:  OutMI.setOpcode(X86::OR16ri8);  goto ReSimplify;
+  case X86::ADD32ri8_DB:  OutMI.setOpcode(X86::OR32ri8);  goto ReSimplify;
+  case X86::ADD64ri8_DB:  OutMI.setOpcode(X86::OR64ri8);  goto ReSimplify;
 
   // Atomic load and store require a separate pseudo-inst because Acquire
   // implies mayStore and Release implies mayLoad; fix these to regular MOV
   // instructions here
-  case X86::ACQUIRE_MOV8rm:
-    OutMI.setOpcode(X86::MOV8rm);
-    goto ReSimplify;
-  case X86::ACQUIRE_MOV16rm:
-    OutMI.setOpcode(X86::MOV16rm);
-    goto ReSimplify;
-  case X86::ACQUIRE_MOV32rm:
-    OutMI.setOpcode(X86::MOV32rm);
-    goto ReSimplify;
-  case X86::ACQUIRE_MOV64rm:
-    OutMI.setOpcode(X86::MOV64rm);
-    goto ReSimplify;
-  case X86::RELEASE_MOV8mr:
-    OutMI.setOpcode(X86::MOV8mr);
-    goto ReSimplify;
-  case X86::RELEASE_MOV16mr:
-    OutMI.setOpcode(X86::MOV16mr);
-    goto ReSimplify;
-  case X86::RELEASE_MOV32mr:
-    OutMI.setOpcode(X86::MOV32mr);
-    goto ReSimplify;
-  case X86::RELEASE_MOV64mr:
-    OutMI.setOpcode(X86::MOV64mr);
-    goto ReSimplify;
-  case X86::RELEASE_MOV8mi:
-    OutMI.setOpcode(X86::MOV8mi);
-    goto ReSimplify;
-  case X86::RELEASE_MOV16mi:
-    OutMI.setOpcode(X86::MOV16mi);
-    goto ReSimplify;
-  case X86::RELEASE_MOV32mi:
-    OutMI.setOpcode(X86::MOV32mi);
-    goto ReSimplify;
-  case X86::RELEASE_MOV64mi32:
-    OutMI.setOpcode(X86::MOV64mi32);
-    goto ReSimplify;
-  case X86::RELEASE_ADD8mi:
-    OutMI.setOpcode(X86::ADD8mi);
-    goto ReSimplify;
-  case X86::RELEASE_ADD8mr:
-    OutMI.setOpcode(X86::ADD8mr);
-    goto ReSimplify;
-  case X86::RELEASE_ADD32mi:
-    OutMI.setOpcode(X86::ADD32mi);
-    goto ReSimplify;
-  case X86::RELEASE_ADD32mr:
-    OutMI.setOpcode(X86::ADD32mr);
-    goto ReSimplify;
-  case X86::RELEASE_ADD64mi32:
-    OutMI.setOpcode(X86::ADD64mi32);
-    goto ReSimplify;
-  case X86::RELEASE_ADD64mr:
-    OutMI.setOpcode(X86::ADD64mr);
-    goto ReSimplify;
-  case X86::RELEASE_AND8mi:
-    OutMI.setOpcode(X86::AND8mi);
-    goto ReSimplify;
-  case X86::RELEASE_AND8mr:
-    OutMI.setOpcode(X86::AND8mr);
-    goto ReSimplify;
-  case X86::RELEASE_AND32mi:
-    OutMI.setOpcode(X86::AND32mi);
-    goto ReSimplify;
-  case X86::RELEASE_AND32mr:
-    OutMI.setOpcode(X86::AND32mr);
-    goto ReSimplify;
-  case X86::RELEASE_AND64mi32:
-    OutMI.setOpcode(X86::AND64mi32);
-    goto ReSimplify;
-  case X86::RELEASE_AND64mr:
-    OutMI.setOpcode(X86::AND64mr);
-    goto ReSimplify;
-  case X86::RELEASE_OR8mi:
-    OutMI.setOpcode(X86::OR8mi);
-    goto ReSimplify;
-  case X86::RELEASE_OR8mr:
-    OutMI.setOpcode(X86::OR8mr);
-    goto ReSimplify;
-  case X86::RELEASE_OR32mi:
-    OutMI.setOpcode(X86::OR32mi);
-    goto ReSimplify;
-  case X86::RELEASE_OR32mr:
-    OutMI.setOpcode(X86::OR32mr);
-    goto ReSimplify;
-  case X86::RELEASE_OR64mi32:
-    OutMI.setOpcode(X86::OR64mi32);
-    goto ReSimplify;
-  case X86::RELEASE_OR64mr:
-    OutMI.setOpcode(X86::OR64mr);
-    goto ReSimplify;
-  case X86::RELEASE_XOR8mi:
-    OutMI.setOpcode(X86::XOR8mi);
-    goto ReSimplify;
-  case X86::RELEASE_XOR8mr:
-    OutMI.setOpcode(X86::XOR8mr);
-    goto ReSimplify;
-  case X86::RELEASE_XOR32mi:
-    OutMI.setOpcode(X86::XOR32mi);
-    goto ReSimplify;
-  case X86::RELEASE_XOR32mr:
-    OutMI.setOpcode(X86::XOR32mr);
-    goto ReSimplify;
-  case X86::RELEASE_XOR64mi32:
-    OutMI.setOpcode(X86::XOR64mi32);
-    goto ReSimplify;
-  case X86::RELEASE_XOR64mr:
-    OutMI.setOpcode(X86::XOR64mr);
-    goto ReSimplify;
-  case X86::RELEASE_INC8m:
-    OutMI.setOpcode(X86::INC8m);
-    goto ReSimplify;
-  case X86::RELEASE_INC16m:
-    OutMI.setOpcode(X86::INC16m);
-    goto ReSimplify;
-  case X86::RELEASE_INC32m:
-    OutMI.setOpcode(X86::INC32m);
-    goto ReSimplify;
-  case X86::RELEASE_INC64m:
-    OutMI.setOpcode(X86::INC64m);
-    goto ReSimplify;
-  case X86::RELEASE_DEC8m:
-    OutMI.setOpcode(X86::DEC8m);
-    goto ReSimplify;
-  case X86::RELEASE_DEC16m:
-    OutMI.setOpcode(X86::DEC16m);
-    goto ReSimplify;
-  case X86::RELEASE_DEC32m:
-    OutMI.setOpcode(X86::DEC32m);
-    goto ReSimplify;
-  case X86::RELEASE_DEC64m:
-    OutMI.setOpcode(X86::DEC64m);
-    goto ReSimplify;
+  case X86::ACQUIRE_MOV8rm:    OutMI.setOpcode(X86::MOV8rm);    goto ReSimplify;
+  case X86::ACQUIRE_MOV16rm:   OutMI.setOpcode(X86::MOV16rm);   goto ReSimplify;
+  case X86::ACQUIRE_MOV32rm:   OutMI.setOpcode(X86::MOV32rm);   goto ReSimplify;
+  case X86::ACQUIRE_MOV64rm:   OutMI.setOpcode(X86::MOV64rm);   goto ReSimplify;
+  case X86::RELEASE_MOV8mr:    OutMI.setOpcode(X86::MOV8mr);    goto ReSimplify;
+  case X86::RELEASE_MOV16mr:   OutMI.setOpcode(X86::MOV16mr);   goto ReSimplify;
+  case X86::RELEASE_MOV32mr:   OutMI.setOpcode(X86::MOV32mr);   goto ReSimplify;
+  case X86::RELEASE_MOV64mr:   OutMI.setOpcode(X86::MOV64mr);   goto ReSimplify;
+  case X86::RELEASE_MOV8mi:    OutMI.setOpcode(X86::MOV8mi);    goto ReSimplify;
+  case X86::RELEASE_MOV16mi:   OutMI.setOpcode(X86::MOV16mi);   goto ReSimplify;
+  case X86::RELEASE_MOV32mi:   OutMI.setOpcode(X86::MOV32mi);   goto ReSimplify;
+  case X86::RELEASE_MOV64mi32: OutMI.setOpcode(X86::MOV64mi32); goto ReSimplify;
+  case X86::RELEASE_ADD8mi:    OutMI.setOpcode(X86::ADD8mi);    goto ReSimplify;
+  case X86::RELEASE_ADD8mr:    OutMI.setOpcode(X86::ADD8mr);    goto ReSimplify;
+  case X86::RELEASE_ADD32mi:   OutMI.setOpcode(X86::ADD32mi);   goto ReSimplify;
+  case X86::RELEASE_ADD32mr:   OutMI.setOpcode(X86::ADD32mr);   goto ReSimplify;
+  case X86::RELEASE_ADD64mi32: OutMI.setOpcode(X86::ADD64mi32); goto ReSimplify;
+  case X86::RELEASE_ADD64mr:   OutMI.setOpcode(X86::ADD64mr);   goto ReSimplify;
+  case X86::RELEASE_AND8mi:    OutMI.setOpcode(X86::AND8mi);    goto ReSimplify;
+  case X86::RELEASE_AND8mr:    OutMI.setOpcode(X86::AND8mr);    goto ReSimplify;
+  case X86::RELEASE_AND32mi:   OutMI.setOpcode(X86::AND32mi);   goto ReSimplify;
+  case X86::RELEASE_AND32mr:   OutMI.setOpcode(X86::AND32mr);   goto ReSimplify;
+  case X86::RELEASE_AND64mi32: OutMI.setOpcode(X86::AND64mi32); goto ReSimplify;
+  case X86::RELEASE_AND64mr:   OutMI.setOpcode(X86::AND64mr);   goto ReSimplify;
+  case X86::RELEASE_OR8mi:     OutMI.setOpcode(X86::OR8mi);     goto ReSimplify;
+  case X86::RELEASE_OR8mr:     OutMI.setOpcode(X86::OR8mr);     goto ReSimplify;
+  case X86::RELEASE_OR32mi:    OutMI.setOpcode(X86::OR32mi);    goto ReSimplify;
+  case X86::RELEASE_OR32mr:    OutMI.setOpcode(X86::OR32mr);    goto ReSimplify;
+  case X86::RELEASE_OR64mi32:  OutMI.setOpcode(X86::OR64mi32);  goto ReSimplify;
+  case X86::RELEASE_OR64mr:    OutMI.setOpcode(X86::OR64mr);    goto ReSimplify;
+  case X86::RELEASE_XOR8mi:    OutMI.setOpcode(X86::XOR8mi);    goto ReSimplify;
+  case X86::RELEASE_XOR8mr:    OutMI.setOpcode(X86::XOR8mr);    goto ReSimplify;
+  case X86::RELEASE_XOR32mi:   OutMI.setOpcode(X86::XOR32mi);   goto ReSimplify;
+  case X86::RELEASE_XOR32mr:   OutMI.setOpcode(X86::XOR32mr);   goto ReSimplify;
+  case X86::RELEASE_XOR64mi32: OutMI.setOpcode(X86::XOR64mi32); goto ReSimplify;
+  case X86::RELEASE_XOR64mr:   OutMI.setOpcode(X86::XOR64mr);   goto ReSimplify;
+  case X86::RELEASE_INC8m:     OutMI.setOpcode(X86::INC8m);     goto ReSimplify;
+  case X86::RELEASE_INC16m:    OutMI.setOpcode(X86::INC16m);    goto ReSimplify;
+  case X86::RELEASE_INC32m:    OutMI.setOpcode(X86::INC32m);    goto ReSimplify;
+  case X86::RELEASE_INC64m:    OutMI.setOpcode(X86::INC64m);    goto ReSimplify;
+  case X86::RELEASE_DEC8m:     OutMI.setOpcode(X86::DEC8m);     goto ReSimplify;
+  case X86::RELEASE_DEC16m:    OutMI.setOpcode(X86::DEC16m);    goto ReSimplify;
+  case X86::RELEASE_DEC32m:    OutMI.setOpcode(X86::DEC32m);    goto ReSimplify;
+  case X86::RELEASE_DEC64m:    OutMI.setOpcode(X86::DEC64m);    goto ReSimplify;
 
   // We don't currently select the correct instruction form for instructions
   // which have a short %eax, etc. form. Handle this by custom lowering, for
@@ -796,181 +649,68 @@ ReSimplify:
   case X86::MOV32rm: {
     unsigned NewOpc;
     switch (OutMI.getOpcode()) {
-    default:
-      llvm_unreachable("Invalid opcode");
+    default: llvm_unreachable("Invalid opcode");
     case X86::MOV8mr_NOREX:
-    case X86::MOV8mr:
-      NewOpc = X86::MOV8o32a;
-      break;
+    case X86::MOV8mr:  NewOpc = X86::MOV8o32a; break;
     case X86::MOV8rm_NOREX:
-    case X86::MOV8rm:
-      NewOpc = X86::MOV8ao32;
-      break;
-    case X86::MOV16mr:
-      NewOpc = X86::MOV16o32a;
-      break;
-    case X86::MOV16rm:
-      NewOpc = X86::MOV16ao32;
-      break;
-    case X86::MOV32mr:
-      NewOpc = X86::MOV32o32a;
-      break;
-    case X86::MOV32rm:
-      NewOpc = X86::MOV32ao32;
-      break;
+    case X86::MOV8rm:  NewOpc = X86::MOV8ao32; break;
+    case X86::MOV16mr: NewOpc = X86::MOV16o32a; break;
+    case X86::MOV16rm: NewOpc = X86::MOV16ao32; break;
+    case X86::MOV32mr: NewOpc = X86::MOV32o32a; break;
+    case X86::MOV32rm: NewOpc = X86::MOV32ao32; break;
     }
     SimplifyShortMoveForm(AsmPrinter, OutMI, NewOpc);
     break;
   }
 
-  case X86::ADC8ri:
-  case X86::ADC16ri:
-  case X86::ADC32ri:
-  case X86::ADC64ri32:
-  case X86::ADD8ri:
-  case X86::ADD16ri:
-  case X86::ADD32ri:
-  case X86::ADD64ri32:
-  case X86::AND8ri:
-  case X86::AND16ri:
-  case X86::AND32ri:
-  case X86::AND64ri32:
-  case X86::CMP8ri:
-  case X86::CMP16ri:
-  case X86::CMP32ri:
-  case X86::CMP64ri32:
-  case X86::OR8ri:
-  case X86::OR16ri:
-  case X86::OR32ri:
-  case X86::OR64ri32:
-  case X86::SBB8ri:
-  case X86::SBB16ri:
-  case X86::SBB32ri:
-  case X86::SBB64ri32:
-  case X86::SUB8ri:
-  case X86::SUB16ri:
-  case X86::SUB32ri:
-  case X86::SUB64ri32:
-  case X86::TEST8ri:
-  case X86::TEST16ri:
-  case X86::TEST32ri:
-  case X86::TEST64ri32:
-  case X86::XOR8ri:
-  case X86::XOR16ri:
-  case X86::XOR32ri:
-  case X86::XOR64ri32: {
+  case X86::ADC8ri: case X86::ADC16ri: case X86::ADC32ri: case X86::ADC64ri32:
+  case X86::ADD8ri: case X86::ADD16ri: case X86::ADD32ri: case X86::ADD64ri32:
+  case X86::AND8ri: case X86::AND16ri: case X86::AND32ri: case X86::AND64ri32:
+  case X86::CMP8ri: case X86::CMP16ri: case X86::CMP32ri: case X86::CMP64ri32:
+  case X86::OR8ri:  case X86::OR16ri:  case X86::OR32ri:  case X86::OR64ri32:
+  case X86::SBB8ri: case X86::SBB16ri: case X86::SBB32ri: case X86::SBB64ri32:
+  case X86::SUB8ri: case X86::SUB16ri: case X86::SUB32ri: case X86::SUB64ri32:
+  case X86::TEST8ri:case X86::TEST16ri:case X86::TEST32ri:case X86::TEST64ri32:
+  case X86::XOR8ri: case X86::XOR16ri: case X86::XOR32ri: case X86::XOR64ri32: {
     unsigned NewOpc;
     switch (OutMI.getOpcode()) {
-    default:
-      llvm_unreachable("Invalid opcode");
-    case X86::ADC8ri:
-      NewOpc = X86::ADC8i8;
-      break;
-    case X86::ADC16ri:
-      NewOpc = X86::ADC16i16;
-      break;
-    case X86::ADC32ri:
-      NewOpc = X86::ADC32i32;
-      break;
-    case X86::ADC64ri32:
-      NewOpc = X86::ADC64i32;
-      break;
-    case X86::ADD8ri:
-      NewOpc = X86::ADD8i8;
-      break;
-    case X86::ADD16ri:
-      NewOpc = X86::ADD16i16;
-      break;
-    case X86::ADD32ri:
-      NewOpc = X86::ADD32i32;
-      break;
-    case X86::ADD64ri32:
-      NewOpc = X86::ADD64i32;
-      break;
-    case X86::AND8ri:
-      NewOpc = X86::AND8i8;
-      break;
-    case X86::AND16ri:
-      NewOpc = X86::AND16i16;
-      break;
-    case X86::AND32ri:
-      NewOpc = X86::AND32i32;
-      break;
-    case X86::AND64ri32:
-      NewOpc = X86::AND64i32;
-      break;
-    case X86::CMP8ri:
-      NewOpc = X86::CMP8i8;
-      break;
-    case X86::CMP16ri:
-      NewOpc = X86::CMP16i16;
-      break;
-    case X86::CMP32ri:
-      NewOpc = X86::CMP32i32;
-      break;
-    case X86::CMP64ri32:
-      NewOpc = X86::CMP64i32;
-      break;
-    case X86::OR8ri:
-      NewOpc = X86::OR8i8;
-      break;
-    case X86::OR16ri:
-      NewOpc = X86::OR16i16;
-      break;
-    case X86::OR32ri:
-      NewOpc = X86::OR32i32;
-      break;
-    case X86::OR64ri32:
-      NewOpc = X86::OR64i32;
-      break;
-    case X86::SBB8ri:
-      NewOpc = X86::SBB8i8;
-      break;
-    case X86::SBB16ri:
-      NewOpc = X86::SBB16i16;
-      break;
-    case X86::SBB32ri:
-      NewOpc = X86::SBB32i32;
-      break;
-    case X86::SBB64ri32:
-      NewOpc = X86::SBB64i32;
-      break;
-    case X86::SUB8ri:
-      NewOpc = X86::SUB8i8;
-      break;
-    case X86::SUB16ri:
-      NewOpc = X86::SUB16i16;
-      break;
-    case X86::SUB32ri:
-      NewOpc = X86::SUB32i32;
-      break;
-    case X86::SUB64ri32:
-      NewOpc = X86::SUB64i32;
-      break;
-    case X86::TEST8ri:
-      NewOpc = X86::TEST8i8;
-      break;
-    case X86::TEST16ri:
-      NewOpc = X86::TEST16i16;
-      break;
-    case X86::TEST32ri:
-      NewOpc = X86::TEST32i32;
-      break;
-    case X86::TEST64ri32:
-      NewOpc = X86::TEST64i32;
-      break;
-    case X86::XOR8ri:
-      NewOpc = X86::XOR8i8;
-      break;
-    case X86::XOR16ri:
-      NewOpc = X86::XOR16i16;
-      break;
-    case X86::XOR32ri:
-      NewOpc = X86::XOR32i32;
-      break;
-    case X86::XOR64ri32:
-      NewOpc = X86::XOR64i32;
-      break;
+    default: llvm_unreachable("Invalid opcode");
+    case X86::ADC8ri:     NewOpc = X86::ADC8i8;    break;
+    case X86::ADC16ri:    NewOpc = X86::ADC16i16;  break;
+    case X86::ADC32ri:    NewOpc = X86::ADC32i32;  break;
+    case X86::ADC64ri32:  NewOpc = X86::ADC64i32;  break;
+    case X86::ADD8ri:     NewOpc = X86::ADD8i8;    break;
+    case X86::ADD16ri:    NewOpc = X86::ADD16i16;  break;
+    case X86::ADD32ri:    NewOpc = X86::ADD32i32;  break;
+    case X86::ADD64ri32:  NewOpc = X86::ADD64i32;  break;
+    case X86::AND8ri:     NewOpc = X86::AND8i8;    break;
+    case X86::AND16ri:    NewOpc = X86::AND16i16;  break;
+    case X86::AND32ri:    NewOpc = X86::AND32i32;  break;
+    case X86::AND64ri32:  NewOpc = X86::AND64i32;  break;
+    case X86::CMP8ri:     NewOpc = X86::CMP8i8;    break;
+    case X86::CMP16ri:    NewOpc = X86::CMP16i16;  break;
+    case X86::CMP32ri:    NewOpc = X86::CMP32i32;  break;
+    case X86::CMP64ri32:  NewOpc = X86::CMP64i32;  break;
+    case X86::OR8ri:      NewOpc = X86::OR8i8;     break;
+    case X86::OR16ri:     NewOpc = X86::OR16i16;   break;
+    case X86::OR32ri:     NewOpc = X86::OR32i32;   break;
+    case X86::OR64ri32:   NewOpc = X86::OR64i32;   break;
+    case X86::SBB8ri:     NewOpc = X86::SBB8i8;    break;
+    case X86::SBB16ri:    NewOpc = X86::SBB16i16;  break;
+    case X86::SBB32ri:    NewOpc = X86::SBB32i32;  break;
+    case X86::SBB64ri32:  NewOpc = X86::SBB64i32;  break;
+    case X86::SUB8ri:     NewOpc = X86::SUB8i8;    break;
+    case X86::SUB16ri:    NewOpc = X86::SUB16i16;  break;
+    case X86::SUB32ri:    NewOpc = X86::SUB32i32;  break;
+    case X86::SUB64ri32:  NewOpc = X86::SUB64i32;  break;
+    case X86::TEST8ri:    NewOpc = X86::TEST8i8;   break;
+    case X86::TEST16ri:   NewOpc = X86::TEST16i16; break;
+    case X86::TEST32ri:   NewOpc = X86::TEST32i32; break;
+    case X86::TEST64ri32: NewOpc = X86::TEST64i32; break;
+    case X86::XOR8ri:     NewOpc = X86::XOR8i8;    break;
+    case X86::XOR16ri:    NewOpc = X86::XOR16i16;  break;
+    case X86::XOR32ri:    NewOpc = X86::XOR32i32;  break;
+    case X86::XOR64ri32:  NewOpc = X86::XOR64i32;  break;
     }
     SimplifyShortImmForm(OutMI, NewOpc);
     break;
@@ -1139,9 +879,7 @@ static unsigned EmitNop(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
     OS.EmitBytes("\x66");
 
   switch (Opc) {
-  default:
-    llvm_unreachable("Unexpected opcode");
-    break;
+  default: llvm_unreachable("Unexpected opcode");
   case X86::NOOP:
     OS.EmitInstruction(MCInstBuilder(Opc), STI);
     break;
@@ -2105,29 +1843,22 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
       break;
     unsigned SrcIdx, MaskIdx;
     switch (MI->getOpcode()) {
-    default:
-      llvm_unreachable("Invalid opcode");
+    default: llvm_unreachable("Invalid opcode");
     case X86::PSHUFBrm:
     case X86::VPSHUFBrm:
     case X86::VPSHUFBYrm:
     case X86::VPSHUFBZ128rm:
     case X86::VPSHUFBZ256rm:
     case X86::VPSHUFBZrm:
-      SrcIdx = 1;
-      MaskIdx = 5;
-      break;
+      SrcIdx = 1; MaskIdx = 5; break;
     case X86::VPSHUFBZ128rmkz:
     case X86::VPSHUFBZ256rmkz:
     case X86::VPSHUFBZrmkz:
-      SrcIdx = 2;
-      MaskIdx = 6;
-      break;
+      SrcIdx = 2; MaskIdx = 6; break;
     case X86::VPSHUFBZ128rmk:
     case X86::VPSHUFBZ256rmk:
     case X86::VPSHUFBZrmk:
-      SrcIdx = 3;
-      MaskIdx = 7;
-      break;
+      SrcIdx = 3; MaskIdx = 7; break;
     }
 
     assert(MI->getNumOperands() >= 6 &&
@@ -2171,54 +1902,35 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
     unsigned SrcIdx, MaskIdx;
     unsigned ElSize;
     switch (MI->getOpcode()) {
-    default:
-      llvm_unreachable("Invalid opcode");
+    default: llvm_unreachable("Invalid opcode");
     case X86::VPERMILPSrm:
     case X86::VPERMILPSYrm:
     case X86::VPERMILPSZ128rm:
     case X86::VPERMILPSZ256rm:
     case X86::VPERMILPSZrm:
-      SrcIdx = 1;
-      MaskIdx = 5;
-      ElSize = 32;
-      break;
+      SrcIdx = 1; MaskIdx = 5; ElSize = 32; break;
     case X86::VPERMILPSZ128rmkz:
     case X86::VPERMILPSZ256rmkz:
     case X86::VPERMILPSZrmkz:
-      SrcIdx = 2;
-      MaskIdx = 6;
-      ElSize = 32;
-      break;
+      SrcIdx = 2; MaskIdx = 6; ElSize = 32; break;
     case X86::VPERMILPSZ128rmk:
     case X86::VPERMILPSZ256rmk:
     case X86::VPERMILPSZrmk:
-      SrcIdx = 3;
-      MaskIdx = 7;
-      ElSize = 32;
-      break;
+      SrcIdx = 3; MaskIdx = 7; ElSize = 32; break;
     case X86::VPERMILPDrm:
     case X86::VPERMILPDYrm:
     case X86::VPERMILPDZ128rm:
     case X86::VPERMILPDZ256rm:
     case X86::VPERMILPDZrm:
-      SrcIdx = 1;
-      MaskIdx = 5;
-      ElSize = 64;
-      break;
+      SrcIdx = 1; MaskIdx = 5; ElSize = 64; break;
     case X86::VPERMILPDZ128rmkz:
     case X86::VPERMILPDZ256rmkz:
     case X86::VPERMILPDZrmkz:
-      SrcIdx = 2;
-      MaskIdx = 6;
-      ElSize = 64;
-      break;
+      SrcIdx = 2; MaskIdx = 6; ElSize = 64; break;
     case X86::VPERMILPDZ128rmk:
     case X86::VPERMILPDZ256rmk:
     case X86::VPERMILPDZrmk:
-      SrcIdx = 3;
-      MaskIdx = 7;
-      ElSize = 64;
-      break;
+      SrcIdx = 3; MaskIdx = 7; ElSize = 64; break;
     }
 
     assert(MI->getNumOperands() >= 6 &&
@@ -2250,16 +1962,9 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
 
     unsigned ElSize;
     switch (MI->getOpcode()) {
-    default:
-      llvm_unreachable("Invalid opcode");
-    case X86::VPERMIL2PSrm:
-    case X86::VPERMIL2PSYrm:
-      ElSize = 32;
-      break;
-    case X86::VPERMIL2PDrm:
-    case X86::VPERMIL2PDYrm:
-      ElSize = 64;
-      break;
+    default: llvm_unreachable("Invalid opcode");
+    case X86::VPERMIL2PSrm: case X86::VPERMIL2PSYrm: ElSize = 32; break;
+    case X86::VPERMIL2PDrm: case X86::VPERMIL2PDYrm: ElSize = 64; break;
     }
 
     const MachineOperand &MaskOp = MI->getOperand(6);
@@ -2361,48 +2066,20 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
       int NumLanes = 1;
       // Override NumLanes for the broadcast instructions.
       switch (MI->getOpcode()) {
-      case X86::VBROADCASTF128:
-        NumLanes = 2;
-        break;
-      case X86::VBROADCASTI128:
-        NumLanes = 2;
-        break;
-      case X86::VBROADCASTF32X4Z256rm:
-        NumLanes = 2;
-        break;
-      case X86::VBROADCASTF32X4rm:
-        NumLanes = 4;
-        break;
-      case X86::VBROADCASTF32X8rm:
-        NumLanes = 2;
-        break;
-      case X86::VBROADCASTF64X2Z128rm:
-        NumLanes = 2;
-        break;
-      case X86::VBROADCASTF64X2rm:
-        NumLanes = 4;
-        break;
-      case X86::VBROADCASTF64X4rm:
-        NumLanes = 2;
-        break;
-      case X86::VBROADCASTI32X4Z256rm:
-        NumLanes = 2;
-        break;
-      case X86::VBROADCASTI32X4rm:
-        NumLanes = 4;
-        break;
-      case X86::VBROADCASTI32X8rm:
-        NumLanes = 2;
-        break;
-      case X86::VBROADCASTI64X2Z128rm:
-        NumLanes = 2;
-        break;
-      case X86::VBROADCASTI64X2rm:
-        NumLanes = 4;
-        break;
-      case X86::VBROADCASTI64X4rm:
-        NumLanes = 2;
-        break;
+      case X86::VBROADCASTF128:        NumLanes = 2; break;
+      case X86::VBROADCASTI128:        NumLanes = 2; break;
+      case X86::VBROADCASTF32X4Z256rm: NumLanes = 2; break;
+      case X86::VBROADCASTF32X4rm:     NumLanes = 4; break;
+      case X86::VBROADCASTF32X8rm:     NumLanes = 2; break;
+      case X86::VBROADCASTF64X2Z128rm: NumLanes = 2; break;
+      case X86::VBROADCASTF64X2rm:     NumLanes = 4; break;
+      case X86::VBROADCASTF64X4rm:     NumLanes = 2; break;
+      case X86::VBROADCASTI32X4Z256rm: NumLanes = 2; break;
+      case X86::VBROADCASTI32X4rm:     NumLanes = 4; break;
+      case X86::VBROADCASTI32X8rm:     NumLanes = 2; break;
+      case X86::VBROADCASTI64X2Z128rm: NumLanes = 2; break;
+      case X86::VBROADCASTI64X2rm:     NumLanes = 4; break;
+      case X86::VBROADCASTI64X4rm:     NumLanes = 2; break;
       }
 
       std::string Comment;
@@ -2478,92 +2155,35 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
     if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
       int NumElts;
       switch (MI->getOpcode()) {
-      default:
-        llvm_unreachable("Invalid opcode");
-      case X86::VBROADCASTSSrm:
-        NumElts = 4;
-        break;
-      case X86::VBROADCASTSSYrm:
-        NumElts = 8;
-        break;
-      case X86::VBROADCASTSSZ128m:
-        NumElts = 4;
-        break;
-      case X86::VBROADCASTSSZ256m:
-        NumElts = 8;
-        break;
-      case X86::VBROADCASTSSZm:
-        NumElts = 16;
-        break;
-      case X86::VBROADCASTSDYrm:
-        NumElts = 4;
-        break;
-      case X86::VBROADCASTSDZ256m:
-        NumElts = 4;
-        break;
-      case X86::VBROADCASTSDZm:
-        NumElts = 8;
-        break;
-      case X86::VPBROADCASTBrm:
-        NumElts = 16;
-        break;
-      case X86::VPBROADCASTBYrm:
-        NumElts = 32;
-        break;
-      case X86::VPBROADCASTBZ128m:
-        NumElts = 16;
-        break;
-      case X86::VPBROADCASTBZ256m:
-        NumElts = 32;
-        break;
-      case X86::VPBROADCASTBZm:
-        NumElts = 64;
-        break;
-      case X86::VPBROADCASTDrm:
-        NumElts = 4;
-        break;
-      case X86::VPBROADCASTDYrm:
-        NumElts = 8;
-        break;
-      case X86::VPBROADCASTDZ128m:
-        NumElts = 4;
-        break;
-      case X86::VPBROADCASTDZ256m:
-        NumElts = 8;
-        break;
-      case X86::VPBROADCASTDZm:
-        NumElts = 16;
-        break;
-      case X86::VPBROADCASTQrm:
-        NumElts = 2;
-        break;
-      case X86::VPBROADCASTQYrm:
-        NumElts = 4;
-        break;
-      case X86::VPBROADCASTQZ128m:
-        NumElts = 2;
-        break;
-      case X86::VPBROADCASTQZ256m:
-        NumElts = 4;
-        break;
-      case X86::VPBROADCASTQZm:
-        NumElts = 8;
-        break;
-      case X86::VPBROADCASTWrm:
-        NumElts = 8;
-        break;
-      case X86::VPBROADCASTWYrm:
-        NumElts = 16;
-        break;
-      case X86::VPBROADCASTWZ128m:
-        NumElts = 8;
-        break;
-      case X86::VPBROADCASTWZ256m:
-        NumElts = 16;
-        break;
-      case X86::VPBROADCASTWZm:
-        NumElts = 32;
-        break;
+      default: llvm_unreachable("Invalid opcode");
+      case X86::VBROADCASTSSrm:    NumElts = 4;  break;
+      case X86::VBROADCASTSSYrm:   NumElts = 8;  break;
+      case X86::VBROADCASTSSZ128m: NumElts = 4;  break;
+      case X86::VBROADCASTSSZ256m: NumElts = 8;  break;
+      case X86::VBROADCASTSSZm:    NumElts = 16; break;
+      case X86::VBROADCASTSDYrm:   NumElts = 4;  break;
+      case X86::VBROADCASTSDZ256m: NumElts = 4;  break;
+      case X86::VBROADCASTSDZm:    NumElts = 8;  break;
+      case X86::VPBROADCASTBrm:    NumElts = 16; break;
+      case X86::VPBROADCASTBYrm:   NumElts = 32; break;
+      case X86::VPBROADCASTBZ128m: NumElts = 16; break;
+      case X86::VPBROADCASTBZ256m: NumElts = 32; break;
+      case X86::VPBROADCASTBZm:    NumElts = 64; break;
+      case X86::VPBROADCASTDrm:    NumElts = 4;  break;
+      case X86::VPBROADCASTDYrm:   NumElts = 8;  break;
+      case X86::VPBROADCASTDZ128m: NumElts = 4;  break;
+      case X86::VPBROADCASTDZ256m: NumElts = 8;  break;
+      case X86::VPBROADCASTDZm:    NumElts = 16; break;
+      case X86::VPBROADCASTQrm:    NumElts = 2;  break;
+      case X86::VPBROADCASTQYrm:   NumElts = 4;  break;
+      case X86::VPBROADCASTQZ128m: NumElts = 2;  break;
+      case X86::VPBROADCASTQZ256m: NumElts = 4;  break;
+      case X86::VPBROADCASTQZm:    NumElts = 8;  break;
+      case X86::VPBROADCASTWrm:    NumElts = 8;  break;
+      case X86::VPBROADCASTWYrm:   NumElts = 16; break;
+      case X86::VPBROADCASTWZ128m: NumElts = 8;  break;
+      case X86::VPBROADCASTWZ256m: NumElts = 16; break;
+      case X86::VPBROADCASTWZm:    NumElts = 32; break;
       }
 
       std::string Comment;