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| author | Scott Michel <scottm@aero.org> | 2009-03-17 16:45:16 +0000 |
|---|---|---|
| committer | Scott Michel <scottm@aero.org> | 2009-03-17 16:45:16 +0000 |
| commit | df52d3d477263e058b8cb63992c85b56caef913d (patch) | |
| tree | ec7955acc2e1166915b6e72acd88b37f2b6cc967 /llvm/lib | |
| parent | af41991c8f924a28353ea0cc936b6e04b881ef31 (diff) | |
| download | bcm5719-llvm-df52d3d477263e058b8cb63992c85b56caef913d.tar.gz bcm5719-llvm-df52d3d477263e058b8cb63992c85b56caef913d.zip | |
CellSPU:
Revert inadvertent mis-fix of fneg.
llvm-svn: 67084
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/CellSPU/SPUInstrInfo.td | 28 |
2 files changed, 16 insertions, 16 deletions
diff --git a/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp index d1486220099..dd2ef6448ca 100644 --- a/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp @@ -865,12 +865,12 @@ SPUDAGToDAGISel::Select(SDValue Op) { SDValue negConst = CurDAG->getConstant(0x8000000000000000ULL, MVT::i64); SDNode *signMask = 0; - unsigned Opc = SPU::ORfneg64; + unsigned Opc = SPU::XORfneg64; if (OpVT == MVT::f64) { signMask = SelectI64Constant(negConst, MVT::i64, dl); } else if (OpVT == MVT::v2f64) { - Opc = SPU::ORfnegvec; + Opc = SPU::XORfnegvec; signMask = emitBuildVector(CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, negConst, negConst)); diff --git a/llvm/lib/Target/CellSPU/SPUInstrInfo.td b/llvm/lib/Target/CellSPU/SPUInstrInfo.td index 86eb61cf86c..63eb85a2921 100644 --- a/llvm/lib/Target/CellSPU/SPUInstrInfo.td +++ b/llvm/lib/Target/CellSPU/SPUInstrInfo.td @@ -1483,17 +1483,6 @@ multiclass BitwiseOr def f64: ORInst<(outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB), [/* no pattern */]>; - // OR instructions used to negate f32 and f64 quantities. - - def fneg32: ORInst<(outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB), - [/* no pattern */]>; - - def fneg64: ORInst<(outs R64FP:$rT), (ins R64FP:$rA, R64C:$rB), - [/* no pattern */]>; - - def fnegvec: ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - [/* no pattern, see fneg{32,64} */]>; - // scalar->vector promotion, prefslot2vec: def v16i8_i8: ORPromoteScalar<R8C>; def v8i16_i16: ORPromoteScalar<R16C>; @@ -1797,6 +1786,17 @@ multiclass BitwiseExclusiveOr def r32: XORRegInst<R32C>; def r16: XORRegInst<R16C>; def r8: XORRegInst<R8C>; + + // XOR instructions used to negate f32 and f64 quantities. + + def fneg32: XORInst<(outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB), + [/* no pattern */]>; + + def fneg64: XORInst<(outs R64FP:$rT), (ins R64FP:$rA, R64C:$rB), + [/* no pattern */]>; + + def fnegvec: XORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [/* no pattern, see fneg{32,64} */]>; } defm XOR : BitwiseExclusiveOr; @@ -4298,11 +4298,11 @@ def FNMAv2f64 : //===----------------------------------------------------------------------==// def : Pat<(fneg (v4f32 VECREG:$rA)), - (ORfnegvec (v4f32 VECREG:$rA), - (v4f32 (ILHUv4i32 0x8000)))>; + (XORfnegvec (v4f32 VECREG:$rA), + (v4f32 (ILHUv4i32 0x8000)))>; def : Pat<(fneg R32FP:$rA), - (ORfneg32 R32FP:$rA, (ILHUr32 0x8000))>; + (XORfneg32 R32FP:$rA, (ILHUr32 0x8000))>; // Floating point absolute value // Note: f64 fabs is custom-selected. |
