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| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-04-06 20:59:59 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-04-06 20:59:59 +0000 |
| commit | df3256aa7f90380ac7f7336a319b55fd1737ea09 (patch) | |
| tree | edd324aef9a40a7e0daddf9225e37d9f9aa072e3 /llvm/lib | |
| parent | bd32728a9819beff64f47771623ee7b9a7fdc863 (diff) | |
| download | bcm5719-llvm-df3256aa7f90380ac7f7336a319b55fd1737ea09.tar.gz bcm5719-llvm-df3256aa7f90380ac7f7336a319b55fd1737ea09.zip | |
fix copy/paste errors, and add imm support to SxADDQ and SxSUBQ
llvm-svn: 21121
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaISelPattern.cpp | 40 |
1 files changed, 32 insertions, 8 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp index 7d3b7cf96cf..d046ce6b4c3 100644 --- a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp @@ -1703,34 +1703,58 @@ unsigned ISel::SelectExpr(SDOperand N) { N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant && cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getValue() == 2) { - Tmp1 = SelectExpr(N.getOperand(1)); Tmp2 = SelectExpr(N.getOperand(0).getOperand(0)); - BuildMI(BB, isAdd?Alpha::S4ADDQ:Alpha::S4SUBQ, 2, Result).addReg(Tmp2).addReg(Tmp1); + if (N.getOperand(1).getOpcode() == ISD::Constant && + cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255) + BuildMI(BB, isAdd?Alpha::S4ADDQi:Alpha::S4SUBQi, 2, Result).addReg(Tmp2) + .addImm(cast<ConstantSDNode>(N.getOperand(1))->getValue()); + else { + Tmp1 = SelectExpr(N.getOperand(1)); + BuildMI(BB, isAdd?Alpha::S4ADDQ:Alpha::S4SUBQ, 2, Result).addReg(Tmp2).addReg(Tmp1); + } } else if(N.getOperand(0).getOpcode() == ISD::SHL && N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant && cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getValue() == 3) { - Tmp1 = SelectExpr(N.getOperand(1)); Tmp2 = SelectExpr(N.getOperand(0).getOperand(0)); - BuildMI(BB, isAdd?Alpha::S4ADDQ:Alpha::S8SUBQ, 2, Result).addReg(Tmp2).addReg(Tmp1); + if (N.getOperand(1).getOpcode() == ISD::Constant && + cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255) + BuildMI(BB, isAdd?Alpha::S8ADDQi:Alpha::S8SUBQi, 2, Result).addReg(Tmp2) + .addImm(cast<ConstantSDNode>(N.getOperand(1))->getValue()); + else { + Tmp1 = SelectExpr(N.getOperand(1)); + BuildMI(BB, isAdd?Alpha::S8ADDQ:Alpha::S8SUBQ, 2, Result).addReg(Tmp2).addReg(Tmp1); + } } //Position prevents subs else if(N.getOperand(1).getOpcode() == ISD::SHL && isAdd & N.getOperand(1).getOperand(1).getOpcode() == ISD::Constant && cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() == 2) { - Tmp1 = SelectExpr(N.getOperand(0)); Tmp2 = SelectExpr(N.getOperand(1).getOperand(0)); - BuildMI(BB, Alpha::S8ADDQ, 2, Result).addReg(Tmp2).addReg(Tmp1); + if (N.getOperand(0).getOpcode() == ISD::Constant && + cast<ConstantSDNode>(N.getOperand(0))->getValue() <= 255) + BuildMI(BB, Alpha::S4ADDQi, 2, Result).addReg(Tmp2) + .addImm(cast<ConstantSDNode>(N.getOperand(0))->getValue()); + else { + Tmp1 = SelectExpr(N.getOperand(0)); + BuildMI(BB, Alpha::S4ADDQ, 2, Result).addReg(Tmp2).addReg(Tmp1); + } } else if(N.getOperand(0).getOpcode() == ISD::SHL && isAdd && N.getOperand(1).getOperand(1).getOpcode() == ISD::Constant && cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() == 3) { - Tmp1 = SelectExpr(N.getOperand(0)); Tmp2 = SelectExpr(N.getOperand(1).getOperand(0)); - BuildMI(BB, Alpha::S8ADDQ, 2, Result).addReg(Tmp2).addReg(Tmp1); + if (N.getOperand(0).getOpcode() == ISD::Constant && + cast<ConstantSDNode>(N.getOperand(0))->getValue() <= 255) + BuildMI(BB, Alpha::S8ADDQi, 2, Result).addReg(Tmp2) + .addImm(cast<ConstantSDNode>(N.getOperand(0))->getValue()); + else { + Tmp1 = SelectExpr(N.getOperand(0)); + BuildMI(BB, Alpha::S8ADDQ, 2, Result).addReg(Tmp2).addReg(Tmp1); + } } //small addi else if(N.getOperand(1).getOpcode() == ISD::Constant && |
