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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-03-14 13:22:56 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-03-14 13:22:56 +0000 |
| commit | de995e6e37d038efcd134dc40c1168a7d023eafc (patch) | |
| tree | 486479f603ebe00d4e86c648b5d1db8f86d8729a /llvm/lib | |
| parent | 0ee4a08c00ab0dd9e99f3d4025d5b29d4290808b (diff) | |
| download | bcm5719-llvm-de995e6e37d038efcd134dc40c1168a7d023eafc.tar.gz bcm5719-llvm-de995e6e37d038efcd134dc40c1168a7d023eafc.zip | |
[X86][SSE] Use WriteFShuffleLd for MOVDDUP/MOVSHDUP/MOVSLDUP reg-mem instructions
They shouldn't be treated as pure loads.
Found while investigating D44428
llvm-svn: 327505
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index 51fbdf835ca..17cc8068078 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -4708,6 +4708,7 @@ let AddedComplexity = 20 in { //===---------------------------------------------------------------------===// // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP //===---------------------------------------------------------------------===// + multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr, ValueType vt, RegisterClass RC, PatFrag mem_frag, X86MemOperand x86memop> { @@ -4718,7 +4719,7 @@ def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src), def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src), !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [(set RC:$dst, (OpNode (mem_frag addr:$src)))], - IIC_SSE_MOV_LH>, Sched<[WriteLoad]>; + IIC_SSE_MOV_LH>, Sched<[WriteFShuffleLd]>; } let Predicates = [HasAVX, NoVLX] in { @@ -4786,10 +4787,10 @@ def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src), [(set VR128:$dst, (v2f64 (X86Movddup (scalar_to_vector (loadf64 addr:$src)))))], - IIC_SSE_MOV_LH>, Sched<[WriteLoad]>; + IIC_SSE_MOV_LH>, Sched<[WriteFShuffleLd]>; } -// FIXME: Merge with above classe when there're patterns for the ymm version +// FIXME: Merge with above classes when there are patterns for the ymm version multiclass sse3_replicate_dfp_y<string OpcodeStr> { def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src), !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), @@ -4799,7 +4800,7 @@ def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src), !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [(set VR256:$dst, (v4f64 (X86Movddup (loadv4f64 addr:$src))))]>, - Sched<[WriteLoad]>; + Sched<[WriteFShuffleLd]>; } let Predicates = [HasAVX, NoVLX] in { |
