diff options
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-03-19 22:19:56 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-03-19 22:19:56 +0000 |
| commit | dd78b8059b0a5a469854e5cb43b74378048c76e0 (patch) | |
| tree | c0f5952b3eab420426e107c6466bb65d1bf506be /llvm/lib | |
| parent | d06ebd93e6340d0e81d830a1163c3367187b3d98 (diff) | |
| download | bcm5719-llvm-dd78b8059b0a5a469854e5cb43b74378048c76e0.tar.gz bcm5719-llvm-dd78b8059b0a5a469854e5cb43b74378048c76e0.zip | |
R600/SI: Add unused LDS 2 form instructions.
llvm-svn: 204275
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/R600/SIInstrInfo.td | 25 | ||||
| -rw-r--r-- | llvm/lib/Target/R600/SIInstructions.td | 11 |
2 files changed, 35 insertions, 1 deletions
diff --git a/llvm/lib/Target/R600/SIInstrInfo.td b/llvm/lib/Target/R600/SIInstrInfo.td index 173f9bbd21c..e05ab65e8b6 100644 --- a/llvm/lib/Target/R600/SIInstrInfo.td +++ b/llvm/lib/Target/R600/SIInstrInfo.td @@ -412,10 +412,22 @@ class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A < let mayStore = 0; } +class DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS < + op, + (outs regClass:$vdst), + (ins i1imm:$gds, VReg_32:$addr, i8imm:$offset0, i8imm:$offset1), + asm#" $gds, $vdst, $addr, $offset0, $offset1, [M0]", + []> { + let data0 = 0; + let data1 = 0; + let mayLoad = 1; + let mayStore = 0; +} + class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A < op, (outs), - (ins i1imm:$gds, VReg_32:$addr, VReg_32:$data0, i16imm:$offset), + (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, i16imm:$offset), asm#" $addr, $data0, $offset [M0]", []> { let data1 = 0; @@ -424,6 +436,17 @@ class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A < let vdst = 0; } +class DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A < + op, + (outs), + (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, i8imm:$offset0, i8imm:$offset1), + asm#" $addr, $data0, $data1, $offset0, $offset1 [M0]", + []> { + let mayStore = 1; + let mayLoad = 0; + let vdst = 0; +} + class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc> : DS_1A < op, (outs rc:$vdst), diff --git a/llvm/lib/Target/R600/SIInstructions.td b/llvm/lib/Target/R600/SIInstructions.td index bbc72bf093a..fb25acaa1cd 100644 --- a/llvm/lib/Target/R600/SIInstructions.td +++ b/llvm/lib/Target/R600/SIInstructions.td @@ -417,6 +417,17 @@ def DS_READ_I16 : DS_Load_Helper <0x0000003b, "DS_READ_I16", VReg_32>; def DS_READ_U16 : DS_Load_Helper <0x0000003c, "DS_READ_U16", VReg_32>; def DS_READ_B64 : DS_Load_Helper <0x00000076, "DS_READ_B64", VReg_64>; +// 2 forms. +def DS_WRITE2_B32 : DS_Load2_Helper <0x0000000E, "DS_WRITE2_B32", VReg_64>; +def DS_WRITE2_B64 : DS_Load2_Helper <0x0000004E, "DS_WRITE2_B64", VReg_128>; + +def DS_READ2_B32 : DS_Load2_Helper <0x00000037, "DS_READ2_B32", VReg_64>; +def DS_READ2_B64 : DS_Load2_Helper <0x00000075, "DS_READ2_B64", VReg_128>; + +// TODO: DS_READ2ST64_B32, DS_READ2ST64_B64, +// DS_WRITE2ST64_B32, DS_WRITE2ST64_B64 + + //def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>; //def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>; //def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>; |
