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| author | Craig Topper <craig.topper@intel.com> | 2018-11-17 02:36:07 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-11-17 02:36:07 +0000 |
| commit | dd61f1164223ff56cd07de0ef98e1cf49e6e653e (patch) | |
| tree | 78c84c3593edcd4cd2d2271081ccf519987fc8aa /llvm/lib | |
| parent | d8da95bbe32c1e1de56a54638ba25eef9f8cc4ca (diff) | |
| download | bcm5719-llvm-dd61f1164223ff56cd07de0ef98e1cf49e6e653e.tar.gz bcm5719-llvm-dd61f1164223ff56cd07de0ef98e1cf49e6e653e.zip | |
[X86] Don't extend v32i8 multiplies to v32i16 with avx512bw and prefer-vector-width=256.
llvm-svn: 347131
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 7bf395ace0c..d4a0572bedd 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -23350,7 +23350,7 @@ static SDValue LowerMUL(SDValue Op, const X86Subtarget &Subtarget, // For 256-bit vectors, split into 128-bit vectors to allow the // sign-extension to occur. We don't need this on AVX512BW as we can // safely sign-extend to v32i16. - if (VT == MVT::v32i8 && !Subtarget.hasBWI()) + if (VT == MVT::v32i8 && !Subtarget.canExtendTo512BW()) return split256IntArith(Op, DAG); MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements()); |
