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authorDan Gohman <gohman@apple.com>2009-04-15 00:10:16 +0000
committerDan Gohman <gohman@apple.com>2009-04-15 00:10:16 +0000
commitdd07f638f5f8966b975dabc35e4db2dc77907348 (patch)
tree5da5ebb73276df92a87e464010b235acf348ab95 /llvm/lib
parentc2223ab255b2a4e5be83c36c66565263cf3c7f9a (diff)
downloadbcm5719-llvm-dd07f638f5f8966b975dabc35e4db2dc77907348.tar.gz
bcm5719-llvm-dd07f638f5f8966b975dabc35e4db2dc77907348.zip
Do for GR16_NOREX what r69049 did for GR8_NOREX, to avoid trouble with
the local register allocator. llvm-svn: 69115
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/X86/X86RegisterInfo.td35
1 files changed, 35 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.td b/llvm/lib/Target/X86/X86RegisterInfo.td
index 7137f6b88a7..a375868c67a 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.td
+++ b/llvm/lib/Target/X86/X86RegisterInfo.td
@@ -537,6 +537,41 @@ def GR8_NOREX : RegisterClass<"X86", [i8], 8,
def GR16_NOREX : RegisterClass<"X86", [i16], 16,
[AX, CX, DX, SI, DI, BX, BP, SP]> {
let SubRegClassList = [GR8_NOREX, GR8_NOREX];
+ let MethodProtos = [{
+ iterator allocation_order_begin(const MachineFunction &MF) const;
+ iterator allocation_order_end(const MachineFunction &MF) const;
+ }];
+ let MethodBodies = [{
+ // Does the function dedicate RBP / EBP to being a frame ptr?
+ // If so, don't allocate SP or BP.
+ static const unsigned X86_GR16_AO_fp[] = {
+ X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX
+ };
+ // If not, just don't allocate SP.
+ static const unsigned X86_GR16_AO[] = {
+ X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP
+ };
+
+ GR16_NOREXClass::iterator
+ GR16_NOREXClass::allocation_order_begin(const MachineFunction &MF) const {
+ const TargetMachine &TM = MF.getTarget();
+ const TargetRegisterInfo *RI = TM.getRegisterInfo();
+ if (RI->hasFP(MF))
+ return X86_GR16_AO_fp;
+ else
+ return X86_GR16_AO;
+ }
+
+ GR16_NOREXClass::iterator
+ GR16_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
+ const TargetMachine &TM = MF.getTarget();
+ const TargetRegisterInfo *RI = TM.getRegisterInfo();
+ if (RI->hasFP(MF))
+ return X86_GR16_AO_fp+(sizeof(X86_GR16_AO_fp)/sizeof(unsigned));
+ else
+ return X86_GR16_AO + (sizeof(X86_GR16_AO) / sizeof(unsigned));
+ }
+ }];
}
// GR32_NOREX - GR32 registers which do not require a REX prefix.
def GR32_NOREX : RegisterClass<"X86", [i32], 32,
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