ARM: support emission of complex SO expressions

Support to the IAS was added to actually parse and handle the complex SO
expressions.  However, the object file lowering was not updated to compensate
for the fact that the shift operand may be an absolute expression.

When trying to assemble to an object file, the lowering would fail while
succeeding when emitting purely assembly.  Add an appropriate test.

The test case is inspired by the test case provided by Jiangning Liu who also
brought the issue to light.

llvm-svn: 203762

1 files changed, 13 insertions, 2 deletions

diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
index 3b2ca73aecd..716b22e3b37 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
@@ -271,8 +271,19 @@ public:
   unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
                            SmallVectorImpl<MCFixup> &Fixups,
                            const MCSubtargetInfo &STI) const {
-    unsigned SoImm = MI.getOperand(Op).getImm();
-    int SoImmVal = ARM_AM::getSOImmVal(SoImm);
+    int SoImmVal = -1;
+
+    const MCOperand &MO = MI.getOperand(Op);
+    if (MO.isImm()) {
+      SoImmVal = ARM_AM::getSOImmVal(MO.getImm());
+    } else if (MO.isExpr()) {
+      int64_t Value;
+      bool Invalid = MO.getExpr()->EvaluateAsAbsolute(Value);
+      assert(!Invalid && "non-constant expression is not a valid SOImm operand");
+      assert((Value >= INT32_MIN && Value <= INT32_MAX) &&
+             "expression must be representable in 32 bits");
+      SoImmVal = Value;
+    }
     assert(SoImmVal != -1 && "Not a valid so_imm value!");
 
     // Encode rotate_imm.