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| author | Tim Northover <Tim.Northover@arm.com> | 2013-04-20 19:31:00 +0000 |
|---|---|---|
| committer | Tim Northover <Tim.Northover@arm.com> | 2013-04-20 19:31:00 +0000 |
| commit | d9d4211fe2b8bbe969820610825ffa7d6d215daa (patch) | |
| tree | 7545cd18689626515fa7a3f5b9772f8cb637a9be /llvm/lib | |
| parent | 36e827602a79ab462177c0c764a1f6b01aa6e87c (diff) | |
| download | bcm5719-llvm-d9d4211fe2b8bbe969820610825ffa7d6d215daa.tar.gz bcm5719-llvm-d9d4211fe2b8bbe969820610825ffa7d6d215daa.zip | |
ARM: don't add FrameIndex offset for LDMIA (has no immediate)
Previously, when spilling 64-bit paired registers, an LDMIA with both
a FrameIndex and an offset was produced. This kind of instruction
shouldn't exist, and the extra operand was being confused with the
predicate, causing aborts later on.
This removes the invalid 0-offset from the instruction being
produced.
llvm-svn: 179956
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index 9e68ff44890..7a8077e3f9e 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -978,7 +978,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA : ARM::LDMIA; MachineInstrBuilder MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(LdmOpc)) - .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); + .addFrameIndex(FI).addMemOperand(MMO)); MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); if (TargetRegisterInfo::isPhysicalRegister(DestReg)) |
