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authorDaniel Sanders <daniel.sanders@imgtec.com>2016-04-18 12:35:36 +0000
committerDaniel Sanders <daniel.sanders@imgtec.com>2016-04-18 12:35:36 +0000
commitd8c07766f36a2ef50e6b5fe1473d14284d1e049f (patch)
tree70e2a6b89bff27793ed0b98fab9c659746367bfc /llvm/lib
parent5bf59728e2461a277f0731b985264224fae2fb0b (diff)
downloadbcm5719-llvm-d8c07766f36a2ef50e6b5fe1473d14284d1e049f.tar.gz
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[mips][ias] Prevent double-filling of delay slots by generating '.set noreorder' regions.
Summary: When clang is given -save-temps or -via-file-asm, any inline assembly in the source is parsed twice. Once by the compiler, and again by the assembler. We must take care to ensure that this doesn't lead to double-filling delay slots. Reviewers: sdardis, vkalintiris Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19166 llvm-svn: 266608
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp9
1 files changed, 8 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 596fcbba470..4fdeeac2855 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -1930,6 +1930,11 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
}
}
+ bool FillDelaySlot =
+ MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder();
+ if (FillDelaySlot)
+ getTargetStreamer().emitDirectiveSetNoReorder();
+
MacroExpanderResultTy ExpandResult =
tryExpandInstruction(Inst, IDLoc, Out, STI);
switch (ExpandResult) {
@@ -1944,8 +1949,10 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
// If this instruction has a delay slot and .set reorder is active,
// emit a NOP after it.
- if (MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder())
+ if (FillDelaySlot) {
createNop(hasShortDelaySlot(Inst.getOpcode()), IDLoc, Out, STI);
+ getTargetStreamer().emitDirectiveSetReorder();
+ }
if ((Inst.getOpcode() == Mips::JalOneReg ||
Inst.getOpcode() == Mips::JalTwoReg || ExpandedJalSym) &&
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