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| author | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2018-03-16 08:06:25 +0000 |
|---|---|---|
| committer | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2018-03-16 08:06:25 +0000 |
| commit | d391a1a985bdca24e38a4a9f0a5559d1218c6fc8 (patch) | |
| tree | 8be6352ec2a11bc1c8ecbbead170b2582a5eaf4d /llvm/lib | |
| parent | 9f373a379d3a1a6b04c8c56af4f560f32449a1de (diff) | |
| download | bcm5719-llvm-d391a1a985bdca24e38a4a9f0a5559d1218c6fc8.tar.gz bcm5719-llvm-d391a1a985bdca24e38a4a9f0a5559d1218c6fc8.zip | |
[ARM] FP16 codegen support for VSEL
This implements lowering of SELECT_CC for f16s, which enables
codegen of VSEL with f16 types.
Differential Revision: https://reviews.llvm.org/D44518
llvm-svn: 327695
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrVFP.td | 4 |
2 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 0c9f615d888..e86e5bce2b6 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -1048,6 +1048,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM, setOperationAction(ISD::SELECT, MVT::i32, Custom); setOperationAction(ISD::SELECT, MVT::f32, Custom); setOperationAction(ISD::SELECT, MVT::f64, Custom); + setOperationAction(ISD::SELECT_CC, MVT::f16, Custom); setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); diff --git a/llvm/lib/Target/ARM/ARMInstrVFP.td b/llvm/lib/Target/ARM/ARMInstrVFP.td index 9efc4f9c343..8731a7fdce9 100644 --- a/llvm/lib/Target/ARM/ARMInstrVFP.td +++ b/llvm/lib/Target/ARM/ARMInstrVFP.td @@ -451,9 +451,9 @@ multiclass vsel_inst<string op, bits<2> opc, int CC> { let DecoderNamespace = "VFPV8", PostEncoderMethod = "", Uses = [CPSR], AddedComplexity = 4 in { def H : AHbInp<0b11100, opc, 0, - (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), + (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), NoItinerary, !strconcat("vsel", op, ".f16\t$Sd, $Sn, $Sm"), - []>, + [(set HPR:$Sd, (ARMcmov HPR:$Sm, HPR:$Sn, CC))]>, Requires<[HasFullFP16]>; def S : ASbInp<0b11100, opc, 0, |
