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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2010-04-07 18:21:58 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2010-04-07 18:21:58 +0000 |
| commit | d351104f1909f8115332816541688862b3d087df (patch) | |
| tree | b5ac90200c5ece03748bdb4cb5bb04f05b5046f9 /llvm/lib | |
| parent | 4acfad7c1b0f704fd72ef72b6c39a34a7ee54446 (diff) | |
| download | bcm5719-llvm-d351104f1909f8115332816541688862b3d087df.tar.gz bcm5719-llvm-d351104f1909f8115332816541688862b3d087df.zip | |
Add some crude approximation for neon load/store instructions
llvm-svn: 100670
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMScheduleV7.td | 56 |
1 files changed, 55 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMScheduleV7.td b/llvm/lib/Target/ARM/ARMScheduleV7.td index 91c6cc3e544..f413aaf1a52 100644 --- a/llvm/lib/Target/ARM/ARMScheduleV7.td +++ b/llvm/lib/Target/ARM/ARMScheduleV7.td @@ -320,30 +320,35 @@ def CortexA8Itineraries : ProcessorItineraries<[ // Issue through integer pipeline, and execute in NEON unit. // // VLD1 + // FIXME: We don't model this instruction properly InstrItinData<IIC_VLD1, [InstrStage<1, [FU_Issue], 0>, InstrStage<1, [FU_Pipe0, FU_Pipe1]>, InstrStage<1, [FU_LdSt0], 0>, InstrStage<1, [FU_NLSPipe]>]>, // // VLD2 + // FIXME: We don't model this instruction properly InstrItinData<IIC_VLD2, [InstrStage<1, [FU_Issue], 0>, InstrStage<1, [FU_Pipe0, FU_Pipe1]>, InstrStage<1, [FU_LdSt0], 0>, InstrStage<1, [FU_NLSPipe]>], [2, 2, 1]>, // // VLD3 + // FIXME: We don't model this instruction properly InstrItinData<IIC_VLD3, [InstrStage<1, [FU_Issue], 0>, InstrStage<1, [FU_Pipe0, FU_Pipe1]>, InstrStage<1, [FU_LdSt0], 0>, InstrStage<1, [FU_NLSPipe]>], [2, 2, 2, 1]>, // // VLD4 + // FIXME: We don't model this instruction properly InstrItinData<IIC_VLD4, [InstrStage<1, [FU_Issue], 0>, InstrStage<1, [FU_Pipe0, FU_Pipe1]>, InstrStage<1, [FU_LdSt0], 0>, InstrStage<1, [FU_NLSPipe]>], [2, 2, 2, 2, 1]>, // // VST + // FIXME: We don't model this instruction properly InstrItinData<IIC_VST, [InstrStage<1, [FU_Issue], 0>, InstrStage<1, [FU_Pipe0, FU_Pipe1]>, InstrStage<1, [FU_LdSt0], 0>, @@ -801,7 +806,56 @@ def CortexA9Itineraries : ProcessorItineraries<[ InstrStage<1, [FU_NPipe]>], [1, 1, 1]>, // NEON // Issue through integer pipeline, and execute in NEON unit. - + // FIXME: Neon pipeline and LdSt unit are multiplexed. + // Add some syntactic sugar to model this! + // VLD1 + // FIXME: We don't model this instruction properly + InstrItinData<IIC_VLD1, [InstrStage<1, [FU_DRegsN], 0, Required>, + InstrStage<7, [FU_DRegsVFP], 0, Reserved>, + InstrStage<1, [FU_Issue], 0>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_LdSt0], 0>, + InstrStage<1, [FU_NPipe]>]>, + // + // VLD2 + // FIXME: We don't model this instruction properly + InstrItinData<IIC_VLD2, [InstrStage<1, [FU_DRegsN], 0, Required>, + // Extra latency cycles since wbck is 6 cycles + InstrStage<7, [FU_DRegsVFP], 0, Reserved>, + InstrStage<1, [FU_Issue], 0>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_LdSt0], 0>, + InstrStage<1, [FU_NPipe]>], [2, 2, 1]>, + // + // VLD3 + // FIXME: We don't model this instruction properly + InstrItinData<IIC_VLD3, [InstrStage<1, [FU_DRegsN], 0, Required>, + // Extra latency cycles since wbck is 6 cycles + InstrStage<7, [FU_DRegsVFP], 0, Reserved>, + InstrStage<1, [FU_Issue], 0>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_LdSt0], 0>, + InstrStage<1, [FU_NPipe]>], [2, 2, 2, 1]>, + // + // VLD4 + // FIXME: We don't model this instruction properly + InstrItinData<IIC_VLD4, [InstrStage<1, [FU_DRegsN], 0, Required>, + // Extra latency cycles since wbck is 6 cycles + InstrStage<7, [FU_DRegsVFP], 0, Reserved>, + InstrStage<1, [FU_Issue], 0>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_LdSt0], 0>, + InstrStage<1, [FU_NPipe]>], [2, 2, 2, 2, 1]>, + // + // VST + // FIXME: We don't model this instruction properly + InstrItinData<IIC_VST, [InstrStage<1, [FU_DRegsN], 0, Required>, + // Extra latency cycles since wbck is 6 cycles + InstrStage<7, [FU_DRegsVFP], 0, Reserved>, + InstrStage<1, [FU_Issue], 0>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_LdSt0], 0>, + InstrStage<1, [FU_NPipe]>]>, // // Double-register Integer Unary InstrItinData<IIC_VUNAiD, [InstrStage<1, [FU_DRegsN], 0, Required>, |
