diff options
| author | Craig Topper <craig.topper@gmail.com> | 2016-12-17 19:26:00 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2016-12-17 19:26:00 +0000 |
| commit | d3295c6a3a8f108c3e2c84dff502747482c39098 (patch) | |
| tree | f60051cc4cc87e23fec342f6a9e3cc7a16919efb /llvm/lib | |
| parent | 81b021e7c0ea5693579d6190bd568bdb2798e9e0 (diff) | |
| download | bcm5719-llvm-d3295c6a3a8f108c3e2c84dff502747482c39098.tar.gz bcm5719-llvm-d3295c6a3a8f108c3e2c84dff502747482c39098.zip | |
[AVX-512] Use EVEX encoded logic operations for scalar types when they are available. This gives the register allocator more registers to work with.
llvm-svn: 290049
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 37 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 2 |
2 files changed, 38 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index bdf21c799da..ac226e6c6ff 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -4559,6 +4559,43 @@ defm : avx512_fp_logical_lowering_sizes<"VPOR", or>; defm : avx512_fp_logical_lowering_sizes<"VPXOR", xor>; defm : avx512_fp_logical_lowering_sizes<"VPANDN", X86andnp>; +let Predicates = [HasDQI] in { + // Use packed logical operations for scalar ops. + def : Pat<(f64 (X86fand FR64X:$src1, FR64X:$src2)), + (COPY_TO_REGCLASS (VANDPDZ128rr + (COPY_TO_REGCLASS FR64X:$src1, VR128X), + (COPY_TO_REGCLASS FR64X:$src2, VR128X)), FR64X)>; + def : Pat<(f64 (X86for FR64X:$src1, FR64X:$src2)), + (COPY_TO_REGCLASS (VORPDZ128rr + (COPY_TO_REGCLASS FR64X:$src1, VR128X), + (COPY_TO_REGCLASS FR64X:$src2, VR128X)), FR64X)>; + def : Pat<(f64 (X86fxor FR64X:$src1, FR64X:$src2)), + (COPY_TO_REGCLASS (VXORPDZ128rr + (COPY_TO_REGCLASS FR64X:$src1, VR128X), + (COPY_TO_REGCLASS FR64X:$src2, VR128X)), FR64X)>; + def : Pat<(f64 (X86fandn FR64X:$src1, FR64X:$src2)), + (COPY_TO_REGCLASS (VANDNPDZ128rr + (COPY_TO_REGCLASS FR64X:$src1, VR128X), + (COPY_TO_REGCLASS FR64X:$src2, VR128X)), FR64X)>; + + def : Pat<(f32 (X86fand FR32X:$src1, FR32X:$src2)), + (COPY_TO_REGCLASS (VANDPSZ128rr + (COPY_TO_REGCLASS FR32X:$src1, VR128X), + (COPY_TO_REGCLASS FR32X:$src2, VR128X)), FR32X)>; + def : Pat<(f32 (X86for FR32X:$src1, FR32X:$src2)), + (COPY_TO_REGCLASS (VORPSZ128rr + (COPY_TO_REGCLASS FR32X:$src1, VR128X), + (COPY_TO_REGCLASS FR32X:$src2, VR128X)), FR32X)>; + def : Pat<(f32 (X86fxor FR32X:$src1, FR32X:$src2)), + (COPY_TO_REGCLASS (VXORPSZ128rr + (COPY_TO_REGCLASS FR32X:$src1, VR128X), + (COPY_TO_REGCLASS FR32X:$src2, VR128X)), FR32X)>; + def : Pat<(f32 (X86fandn FR32X:$src1, FR32X:$src2)), + (COPY_TO_REGCLASS (VANDNPSZ128rr + (COPY_TO_REGCLASS FR32X:$src1, VR128X), + (COPY_TO_REGCLASS FR32X:$src2, VR128X)), FR32X)>; +} + multiclass avx512_fp_scalef_p<bits<8> opc, string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> { defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst), diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index 9a54e98f771..6f344fcd7d6 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -2932,7 +2932,7 @@ let Predicates = [HasAVX, NoVLX_Or_NoDQI] in { (VANDNPDYrm VR256:$src1, addr:$src2)>; } -let Predicates = [HasAVX] in { +let Predicates = [HasAVX, NoDQI] in { // Use packed logical operations for scalar ops. def : Pat<(f64 (X86fand FR64:$src1, FR64:$src2)), (COPY_TO_REGCLASS (VANDPDrr |
