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| author | Evandro Menezes <e.menezes@samsung.com> | 2016-05-04 20:47:25 +0000 |
|---|---|---|
| committer | Evandro Menezes <e.menezes@samsung.com> | 2016-05-04 20:47:25 +0000 |
| commit | d23324aab120afa7d348b813910a677ab7c698dc (patch) | |
| tree | c14942439206a7d1e3c5b4e4cbca54e18501b037 /llvm/lib | |
| parent | a4076ea8a26dc837ee1321de2713d2d35ffad609 (diff) | |
| download | bcm5719-llvm-d23324aab120afa7d348b813910a677ab7c698dc.tar.gz bcm5719-llvm-d23324aab120afa7d348b813910a677ab7c698dc.zip | |
[AArch64] Add cheap as move instructions for Exynos M1
llvm-svn: 268549
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 35 |
1 files changed, 33 insertions, 2 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index 46d90abbe2a..b09cfc0ff55 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -545,9 +545,11 @@ static bool canBeExpandedToORR(const MachineInstr *MI, unsigned BitSize) { // micro-architecture target hook should be introduced here in future. bool AArch64InstrInfo::isAsCheapAsAMove(const MachineInstr *MI) const { if (!Subtarget.isCortexA57() && !Subtarget.isCortexA53() && - !Subtarget.isKryo()) + !Subtarget.isExynosM1() && !Subtarget.isKryo()) return MI->isAsCheapAsAMove(); + unsigned Imm; + switch (MI->getOpcode()) { default: return false; @@ -557,7 +559,17 @@ bool AArch64InstrInfo::isAsCheapAsAMove(const MachineInstr *MI) const { case AArch64::ADDXri: case AArch64::SUBWri: case AArch64::SUBXri: - return (MI->getOperand(3).getImm() == 0); + return (Subtarget.isExynosM1() || + MI->getOperand(3).getImm() == 0); + + // add/sub on register with shift + case AArch64::ADDWrs: + case AArch64::ADDXrs: + case AArch64::SUBWrs: + case AArch64::SUBXrs: + Imm = MI->getOperand(3).getImm(); + return (Subtarget.isExynosM1() && + AArch64_AM::getArithShiftValue(Imm) < 4); // logical ops on immediate case AArch64::ANDWri: @@ -582,6 +594,25 @@ bool AArch64InstrInfo::isAsCheapAsAMove(const MachineInstr *MI) const { case AArch64::ORRWrr: case AArch64::ORRXrr: return true; + + // logical ops on register with shift + case AArch64::ANDWrs: + case AArch64::ANDXrs: + case AArch64::BICWrs: + case AArch64::BICXrs: + case AArch64::EONWrs: + case AArch64::EONXrs: + case AArch64::EORWrs: + case AArch64::EORXrs: + case AArch64::ORNWrs: + case AArch64::ORNXrs: + case AArch64::ORRWrs: + case AArch64::ORRXrs: + Imm = MI->getOperand(3).getImm(); + return (Subtarget.isExynosM1() && + AArch64_AM::getShiftValue(Imm) < 4 && + AArch64_AM::getShiftType(Imm) == AArch64_AM::LSL); + // If MOVi32imm or MOVi64imm can be expanded into ORRWri or // ORRXri, it is as cheap as MOV case AArch64::MOVi32imm: |
