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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-01-31 02:34:03 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-01-31 02:34:03 +0000 |
| commit | d1bfc8d0c3a89124464e92fddd8f5991e7975dd2 (patch) | |
| tree | c8937e455e6967b27b3ec68e91057b10f8878ad1 /llvm/lib | |
| parent | cf4db733d83cc347e40bfc57ad787dccf2f37da7 (diff) | |
| download | bcm5719-llvm-d1bfc8d0c3a89124464e92fddd8f5991e7975dd2.tar.gz bcm5719-llvm-d1bfc8d0c3a89124464e92fddd8f5991e7975dd2.zip | |
GlobalISel: Implement narrowScalar for bswap
llvm-svn: 352719
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 25 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 6 |
2 files changed, 30 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index f8f39be96d6..08ea4d90f12 100644 --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -948,7 +948,31 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) { Observer.changedInstr(MI); return Legalized; } + case TargetOpcode::G_BSWAP: { + Observer.changingInstr(MI); + unsigned DstReg = MI.getOperand(0).getReg(); + + unsigned ShrReg = MRI.createGenericVirtualRegister(WideTy); + unsigned DstExt = MRI.createGenericVirtualRegister(WideTy); + unsigned ShiftAmtReg = MRI.createGenericVirtualRegister(WideTy); + widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); + + MI.getOperand(0).setReg(DstExt); + MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); + + LLT Ty = MRI.getType(DstReg); + unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits(); + MIRBuilder.buildConstant(ShiftAmtReg, DiffBits); + MIRBuilder.buildInstr(TargetOpcode::G_LSHR) + .addDef(ShrReg) + .addUse(DstExt) + .addUse(ShiftAmtReg); + + MIRBuilder.buildTrunc(DstReg, ShrReg); + Observer.changedInstr(MI); + return Legalized; + } case TargetOpcode::G_ADD: case TargetOpcode::G_AND: case TargetOpcode::G_MUL: @@ -1879,6 +1903,7 @@ LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx, case G_FCOS: case G_FSIN: case G_FSQRT: + case G_BSWAP: return fewerElementsVectorBasic(MI, TypeIdx, NarrowTy); case G_ZEXT: case G_SEXT: diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index cf1c075c6f8..7f392952f7e 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -220,8 +220,12 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST, .clampScalar(1, S32, S64); // TODO: Scalarize + // TODO: Expand for > s32 + getActionDefinitionsBuilder(G_BSWAP) + .legalFor({S32}) + .clampScalar(0, S32, S32) + .scalarize(0); - setAction({G_BSWAP, S32}, Legal); getActionDefinitionsBuilder(G_INTTOPTR) .legalIf([](const LegalityQuery &Query) { |
