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authorChris Lattner <sabre@nondot.org>2010-02-17 18:42:24 +0000
committerChris Lattner <sabre@nondot.org>2010-02-17 18:42:24 +0000
commitcb80e2527e2618bf610e50b1de7564bc288136e1 (patch)
treeed69bfc4c09ea684fc9192a2299ebacc2fd38e86 /llvm/lib
parentdf048a962bcd5eb0c38fd95e716f4c8409c89173 (diff)
downloadbcm5719-llvm-cb80e2527e2618bf610e50b1de7564bc288136e1.tar.gz
bcm5719-llvm-cb80e2527e2618bf610e50b1de7564bc288136e1.zip
add a note, from PR5100
llvm-svn: 96490
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/ARM/README.txt2
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/README.txt b/llvm/lib/Target/ARM/README.txt
index 9efb5a1426a..57b65cf15d0 100644
--- a/llvm/lib/Target/ARM/README.txt
+++ b/llvm/lib/Target/ARM/README.txt
@@ -10,6 +10,8 @@ Reimplement 'select' in terms of 'SEL'.
* Implement pre/post increment support. (e.g. PR935)
* Implement smarter constant generation for binops with large immediates.
+A few ARMv6T2 ops should be pattern matched: BFI, SBFX, and UBFX
+
//===---------------------------------------------------------------------===//
Crazy idea: Consider code that uses lots of 8-bit or 16-bit values. By the
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