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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-10-21 17:23:04 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-10-21 17:23:04 +0000 |
| commit | cb028c73214c0ce18ed1fe76e2417c961f0389c9 (patch) | |
| tree | 8a4e0fa8a182eba7b7d08cd1f7a4ba25a5ebf929 /llvm/lib | |
| parent | c7b749bd06824ad9bfb81bc159496b5361cd1ea5 (diff) | |
| download | bcm5719-llvm-cb028c73214c0ce18ed1fe76e2417c961f0389c9.tar.gz bcm5719-llvm-cb028c73214c0ce18ed1fe76e2417c961f0389c9.zip | |
Fix MSVC 'result of 32-bit shift implicitly converted to 64 bits' warning. NFCI.
llvm-svn: 316271
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index 946f99cdb52..b23da692498 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -1298,7 +1298,7 @@ inline bool HexagonDAGToDAGISel::SelectAnyInt(SDValue &N, SDValue &R) { bool HexagonDAGToDAGISel::SelectAnyImmediate(SDValue &N, SDValue &R, uint32_t LogAlign) { auto IsAligned = [LogAlign] (uint64_t V) -> bool { - return alignTo(V, 1u << LogAlign) == V; + return alignTo(V, (uint64_t)1 << LogAlign) == V; }; switch (N.getOpcode()) { @@ -1342,7 +1342,7 @@ bool HexagonDAGToDAGISel::SelectAnyImmediate(SDValue &N, SDValue &R, bool HexagonDAGToDAGISel::SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP, uint32_t LogAlign) { auto IsAligned = [LogAlign] (uint64_t V) -> bool { - return alignTo(V, 1u << LogAlign) == V; + return alignTo(V, (uint64_t)1 << LogAlign) == V; }; switch (N.getOpcode()) { |
