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authorQuentin Colombet <qcolombet@apple.com>2016-04-07 22:35:03 +0000
committerQuentin Colombet <qcolombet@apple.com>2016-04-07 22:35:03 +0000
commitc8d612f6fdb8e1182b62a24b610c964f844bf593 (patch)
treedef33ba05d645291f46562a78b3e3198243a8518 /llvm/lib
parent2445dc19168a4f188bc48746841d1a0105cc258e (diff)
downloadbcm5719-llvm-c8d612f6fdb8e1182b62a24b610c964f844bf593.tar.gz
bcm5719-llvm-c8d612f6fdb8e1182b62a24b610c964f844bf593.zip
[RegisterBankInfo] Introduce getRegBankFromConstraints as an helper
method. NFC. The refactoring intends to make the code more readable and expose more features to potential derived classes. llvm-svn: 265735
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp54
1 files changed, 34 insertions, 20 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
index e068093aeeb..72064e1d6aa 100644
--- a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
@@ -195,6 +195,23 @@ RegisterBankInfo::getRegBank(unsigned Reg, const MachineRegisterInfo &MRI,
return nullptr;
}
+const RegisterBank *RegisterBankInfo::getRegBankFromConstraints(
+ const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII,
+ const TargetRegisterInfo &TRI) const {
+ // The mapping of the registers may be available via the
+ // register class constraints.
+ const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, &TRI);
+
+ if (!RC)
+ return nullptr;
+
+ const RegisterBank &RegBank = getRegBankFromRegClass(*RC);
+ // Sanity check that the target properly implemented getRegBankFromRegClass.
+ assert(RegBank.covers(*RC) &&
+ "The mapping of the register bank does not make sense");
+ return &RegBank;
+}
+
RegisterBankInfo::InstructionMapping
RegisterBankInfo::getInstrMappingImpl(const MachineInstr &MI) const {
RegisterBankInfo::InstructionMapping Mapping(DefaultMappingID, /*Cost*/ 1,
@@ -225,26 +242,23 @@ RegisterBankInfo::getInstrMappingImpl(const MachineInstr &MI) const {
continue;
const RegisterBank *CurRegBank = getRegBank(Reg, MRI, TRI);
if (!CurRegBank) {
- // The mapping of the registers may be available via the
- // register class constraints.
- const TargetRegisterClass *RC =
- MI.getRegClassConstraint(OpIdx, &TII, &TRI);
-
- if (RC)
- CurRegBank = &getRegBankFromRegClass(*RC);
- }
- if (!CurRegBank) {
- CompleteMapping = false;
-
- if (!isCopyLike)
- // MI does not carry enough information to guess the mapping.
- return InstructionMapping();
-
- // For copies, we want to keep interating to find a register
- // bank for the other operands if we did not find one yet.
- if(RegBank)
- break;
- continue;
+ // If this is a target specific instruction, we can deduce
+ // the register bank from the encoding constraints.
+ CurRegBank = getRegBankFromConstraints(MI, OpIdx, TII, TRI);
+ if (!CurRegBank) {
+ // All our attempts failed, give up.
+ CompleteMapping = false;
+
+ if (!isCopyLike)
+ // MI does not carry enough information to guess the mapping.
+ return InstructionMapping();
+
+ // For copies, we want to keep interating to find a register
+ // bank for the other operands if we did not find one yet.
+ if (RegBank)
+ break;
+ continue;
+ }
}
RegBank = CurRegBank;
RegSize = getSizeInBits(Reg, MRI, TRI);
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