ARM/MC/ELF TPsoft is now a proper pseudo inst.

Added test to check bl __aeabi_read_tp gets emitted properly for ELF/ASM
as well as ELF/OBJ (including fixup)

Also added support for ELF::R_ARM_TLS_IE32

llvm-svn: 121312

3 files changed, 31 insertions, 9 deletions

diff --git a/llvm/lib/MC/ELFObjectWriter.cpp b/llvm/lib/MC/ELFObjectWriter.cpp
index 4e0d5ed3950..0b4d0428814 100644
--- a/llvm/lib/MC/ELFObjectWriter.cpp
+++ b/llvm/lib/MC/ELFObjectWriter.cpp
@@ -1533,6 +1533,7 @@ unsigned ARMELFObjectWriter::GetRelocType(const MCValue &Target,
   MCSymbolRefExpr::VariantKind Modifier = Target.isAbsolute() ?
     MCSymbolRefExpr::VK_None : Target.getSymA()->getKind();
 
+  unsigned Type = 0;
   if (IsPCRel) {
     switch (Modifier) {
     default: assert(0 && "Unimplemented Modifier");
@@ -1540,11 +1541,17 @@ unsigned ARMELFObjectWriter::GetRelocType(const MCValue &Target,
     }
     switch ((unsigned)Fixup.getKind()) {
     default: assert(0 && "Unimplemented");
-    case ARM::fixup_arm_branch: return ELF::R_ARM_CALL; break;
+    case ARM::fixup_arm_branch: Type = ELF::R_ARM_CALL; break;
     }
   } else {
     switch ((unsigned)Fixup.getKind()) {
     default: llvm_unreachable("invalid fixup kind!");
+    case FK_Data_4:
+      switch (Modifier) {
+      default: llvm_unreachable("Unsupported Modifier");
+      case MCSymbolRefExpr::VK_ARM_GOTTPOFF:
+        Type = ELF::R_ARM_TLS_IE32;
+      } break;
     case ARM::fixup_arm_ldst_pcrel_12:
     case ARM::fixup_arm_pcrel_10:
     case ARM::fixup_arm_adr_pcrel_12:
@@ -1553,17 +1560,18 @@ unsigned ARMELFObjectWriter::GetRelocType(const MCValue &Target,
     case ARM::fixup_arm_thumb_cp:
       assert(0 && "Unimplemented"); break;
     case ARM::fixup_arm_branch:
-      return ELF::R_ARM_CALL; break;
+      Type = ELF::R_ARM_CALL; break;
     case ARM::fixup_arm_movt_hi16: 
-      return ELF::R_ARM_MOVT_ABS; break;
+      Type = ELF::R_ARM_MOVT_ABS; break;
     case ARM::fixup_arm_movw_lo16:
-      return ELF::R_ARM_MOVW_ABS_NC; break;
+      Type = ELF::R_ARM_MOVW_ABS_NC; break;
     }
   }
 
   if (RelocNeedsGOT(Modifier))
     NeedsGOT = true;
-  return -1;
+  
+  return Type;
 }
 
 //===- MBlazeELFObjectWriter -------------------------------------------===//
diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index ca7a90aa12f..d3b00a4c5ad 100644
--- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -699,6 +699,21 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
       MI.eraseFromParent();
       break;
     }
+    case ARM::TPsoft: {
+      unsigned PredReg = 0;
+      ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg);
+      MachineInstrBuilder MIB = 
+        BuildMI(MBB, MBBI, MI.getDebugLoc(),
+                TII->get(ARM::BL))
+        .addExternalSymbol("__aeabi_read_tp", 0);
+
+      (*MIB).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
+      TransferImpOps(MI, MIB, MIB);
+      MI.eraseFromParent();
+       
+      //assert(0 && "HELP!");
+    }; break;
+
     case ARM::t2LDRHpci:
     case ARM::t2LDRBpci:
     case ARM::t2LDRSHpci:
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index 4c7cdd76395..f9f37df1383 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -3249,12 +3249,11 @@ def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
 //
 
 // __aeabi_read_tp preserves the registers r1-r3.
-// FIXME: This needs to be a pseudo of some sort so that we can get the
-// encoding right, complete with fixup for the aeabi_read_tp function.
+// This is a pseudo inst so that we can get the encoding right, 
+// complete with fixup for the aeabi_read_tp function.
 let isCall = 1,
   Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
-  def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
-               "bl\t__aeabi_read_tp",
+  def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
                [(set R0, ARMthread_pointer)]>;
 }