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| author | Craig Topper <craig.topper@intel.com> | 2018-10-12 22:00:00 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-10-12 22:00:00 +0000 |
| commit | c693a23025c1038f6896666e15df864998358ce2 (patch) | |
| tree | 017d9e24deadeae0c209051bb5d10a1b81c42bde /llvm/lib | |
| parent | a8a44f1becf80e1bc40344c05149d2f94223b5dd (diff) | |
| download | bcm5719-llvm-c693a23025c1038f6896666e15df864998358ce2.tar.gz bcm5719-llvm-c693a23025c1038f6896666e15df864998358ce2.zip | |
[X86] Simplify the end of custom type legalization for (v2i32/v4i16/v8i8 (bitcast (f64))) by just emitting an EXTRACT_SUBVECTOR instead of a BUILD_VECTOR.
Generic legalization should be able to finish legalizing the EXTRACT_SUBVECTOR probably by turning it into a BUILD_VECTOR. But we should emit the simplest sequence.
llvm-svn: 344424
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 220e2e2fdc0..ffb5acf3386 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -26307,13 +26307,9 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N, SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, N->getOperand(0)); SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded); - - SmallVector<SDValue, 8> Elts; - for (unsigned i = 0, e = NumElts; i != e; ++i) - Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, - ToVecInt, DAG.getIntPtrConstant(i, dl))); - - Results.push_back(DAG.getBuildVector(DstVT, dl, Elts)); + SDValue Extract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, + ToVecInt, DAG.getIntPtrConstant(0, dl)); + Results.push_back(Extract); return; } case ISD::MGATHER: { |
