summaryrefslogtreecommitdiffstats
path: root/llvm/lib
diff options
context:
space:
mode:
authorRichard Sandiford <rsandifo@linux.vnet.ibm.com>2013-07-19 16:26:39 +0000
committerRichard Sandiford <rsandifo@linux.vnet.ibm.com>2013-07-19 16:26:39 +0000
commitc575df6dccd66e26b4cede8d06c8b195d7525f30 (patch)
tree9b5563dcad8274e12021af14ea1452c570964ba9 /llvm/lib
parentc57e586792504cb7582dbfbc77d8ae746a02e285 (diff)
downloadbcm5719-llvm-c575df6dccd66e26b4cede8d06c8b195d7525f30.tar.gz
bcm5719-llvm-c575df6dccd66e26b4cede8d06c8b195d7525f30.zip
[SystemZ] Add ARK, AGRK, SRK and SGRK
The testsuite changes follow the same lines as for r186683. llvm-svn: 186686
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/SystemZ/SystemZInstrInfo.td8
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index 5ae6af23aec..fe2b5367fc2 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -535,8 +535,8 @@ def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm),
let Defs = [CC] in {
// Addition of a register.
let isCommutable = 1 in {
- def AR : BinaryRR <"a", 0x1A, add, GR32, GR32>;
- def AGR : BinaryRRE<"ag", 0xB908, add, GR64, GR64>;
+ defm AR : BinaryRRAndK<"a", 0x1A, 0xB9F8, add, GR32, GR32>;
+ defm AGR : BinaryRREAndK<"ag", 0xB908, 0xB9E8, add, GR64, GR64>;
}
def AGFR : BinaryRRE<"agf", 0xB918, null_frag, GR64, GR32>;
@@ -599,9 +599,9 @@ let Defs = [CC], Uses = [CC] in {
// add-immediate instruction instead.
let Defs = [CC] in {
// Subtraction of a register.
- def SR : BinaryRR <"s", 0x1B, sub, GR32, GR32>;
+ defm SR : BinaryRRAndK<"s", 0x1B, 0xB9F9, sub, GR32, GR32>;
def SGFR : BinaryRRE<"sgf", 0xB919, null_frag, GR64, GR32>;
- def SGR : BinaryRRE<"sg", 0xB909, sub, GR64, GR64>;
+ defm SGR : BinaryRREAndK<"sg", 0xB909, 0xB9E9, sub, GR64, GR64>;
// Subtraction of memory.
defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, sextloadi16, 2>;
OpenPOWER on IntegriCloud