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| author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2014-10-17 17:27:06 +0000 |
|---|---|---|
| committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2014-10-17 17:27:06 +0000 |
| commit | c48cb86f05ef43082f8ed4055219b2e6724e21ab (patch) | |
| tree | 4b91ad257057ea5c99a3ed7408d4643b541bdb8e /llvm/lib | |
| parent | e8aab7480c2550b51fd60d6eb102b361e70931d7 (diff) | |
| download | bcm5719-llvm-c48cb86f05ef43082f8ed4055219b2e6724e21ab.tar.gz bcm5719-llvm-c48cb86f05ef43082f8ed4055219b2e6724e21ab.zip | |
[X86] Fix missed selection of non-temporal store of zero vector.
When the input to a store instruction was a zero vector, the backend
always selected a normal vector store regardless of the non-temporal
hint. This is fixed by this patch.
This fixes PR19370.
llvm-svn: 220054
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index 4b283a2988a..3874c1968b5 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -3939,6 +3939,14 @@ def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), PS, Requires<[HasSSE2]>; } // SchedRW = [WriteStore] +let Predicates = [HasAVX, NoVLX] in { + def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst), + (VMOVNTPSmr addr:$dst, VR128:$src)>; +} + +def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst), + (MOVNTPSmr addr:$dst, VR128:$src)>; + } // AddedComplexity //===----------------------------------------------------------------------===// |
