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| author | Craig Topper <craig.topper@intel.com> | 2018-01-23 14:09:22 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-01-23 14:09:22 +0000 |
| commit | c2df6409c70563e1601c43500a4a7aeef454d438 (patch) | |
| tree | 5b183291e9db77d3ff6a323f7c488abd963a83ca /llvm/lib | |
| parent | 69ea82968a9800fd5df073cc7ca2a92a58d74f59 (diff) | |
| download | bcm5719-llvm-c2df6409c70563e1601c43500a4a7aeef454d438.tar.gz bcm5719-llvm-c2df6409c70563e1601c43500a4a7aeef454d438.zip | |
[X86] Add missing MOVSX/MOVZX instructions to load folding tables.
I'm not sure there's any way to generate these folding cases especially the movzx ones since even the register form is never emitted by codegen.
I'm just adding them to remove the difference with the autogenerated version of the folding table.
llvm-svn: 323200
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index de1a3b47970..549b29bfc22 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -616,6 +616,7 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI) { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 }, { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 }, { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 }, + { X86::MOVSX32_NOREXrr8, X86::MOVSX32_NOREXrm8, 0 }, { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 }, { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 }, { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 }, @@ -627,6 +628,8 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI) { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 }, { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 }, { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 }, + { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 }, + { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 }, { X86::PABSBrr, X86::PABSBrm, TB_ALIGN_16 }, { X86::PABSDrr, X86::PABSDrm, TB_ALIGN_16 }, { X86::PABSWrr, X86::PABSWrm, TB_ALIGN_16 }, |
