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| author | Craig Topper <craig.topper@gmail.com> | 2017-02-20 00:37:23 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2017-02-20 00:37:23 +0000 |
| commit | c184b671d933c5f64fd01482e34c8646580b142e (patch) | |
| tree | 8d807aca715004f7e839a5e89119be19871c10ef /llvm/lib | |
| parent | 0f14411b5737a6d6c3d17277b1cadef6306191aa (diff) | |
| download | bcm5719-llvm-c184b671d933c5f64fd01482e34c8646580b142e.tar.gz bcm5719-llvm-c184b671d933c5f64fd01482e34c8646580b142e.zip | |
[X86] Use memory form of shift right by 1 when the rotl immediate is one less than the operation size.
An earlier commit already did this for the register form.
llvm-svn: 295626
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrShiftRotate.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86InstrShiftRotate.td b/llvm/lib/Target/X86/X86InstrShiftRotate.td index b7b77e73b43..8291ba0dc39 100644 --- a/llvm/lib/Target/X86/X86InstrShiftRotate.td +++ b/llvm/lib/Target/X86/X86InstrShiftRotate.td @@ -662,19 +662,19 @@ def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, u8imm:$src), // Rotate by 1 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst), "ror{b}\t$dst", - [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)], + [(store (rotl (loadi8 addr:$dst), (i8 7)), addr:$dst)], IIC_SR>; def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst), "ror{w}\t$dst", - [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)], + [(store (rotl (loadi16 addr:$dst), (i8 15)), addr:$dst)], IIC_SR>, OpSize16; def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst), "ror{l}\t$dst", - [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)], + [(store (rotl (loadi32 addr:$dst), (i8 31)), addr:$dst)], IIC_SR>, OpSize32; def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst), "ror{q}\t$dst", - [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)], + [(store (rotl (loadi64 addr:$dst), (i8 63)), addr:$dst)], IIC_SR>; } // SchedRW |
