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| author | Craig Topper <craig.topper@intel.com> | 2017-12-28 19:46:06 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-12-28 19:46:06 +0000 |
| commit | c0b6cb1e47fca851e4158729b1e4c81abd26028e (patch) | |
| tree | 65edcbfad95c1424a4f1f2b28009e741bba95881 /llvm/lib | |
| parent | 4b311da3a4ef37b4140d78a541e4467cefc2f3a4 (diff) | |
| download | bcm5719-llvm-c0b6cb1e47fca851e4158729b1e4c81abd26028e.tar.gz bcm5719-llvm-c0b6cb1e47fca851e4158729b1e4c81abd26028e.zip | |
[X86] Use ISD::CONCAT_VECTORS when splitting 256-bit loads in combineLoad.
llvm-svn: 321537
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 08cf57b4209..fc18c24048e 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -34057,9 +34057,7 @@ static SDValue combineLoad(SDNode *N, SelectionDAG &DAG, Load1.getValue(1), Load2.getValue(1)); - SDValue NewVec = DAG.getUNDEF(RegVT); - NewVec = insert128BitVector(NewVec, Load1, 0, DAG, dl); - NewVec = insert128BitVector(NewVec, Load2, NumElems / 2, DAG, dl); + SDValue NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Load1, Load2); return DCI.CombineTo(N, NewVec, TF, true); } |
