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authorSean Fertile <sfertile@ca.ibm.com>2019-02-12 17:48:22 +0000
committerSean Fertile <sfertile@ca.ibm.com>2019-02-12 17:48:22 +0000
commitc069452027267151f7edc699de1295830204539e (patch)
tree5f8ccde0cc19ffb4f6d015e3d46dfb37580ddda2 /llvm/lib
parentacbb7ca26c657446124b117c1af7bfaaa524c0a3 (diff)
downloadbcm5719-llvm-c069452027267151f7edc699de1295830204539e.tar.gz
bcm5719-llvm-c069452027267151f7edc699de1295830204539e.zip
[PowerPC] Fix printing of negative offsets in call instruction dissasembly.
llvm-svn: 353865
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp8
-rw-r--r--llvm/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp7
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrInfo.td2
3 files changed, 15 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
index 8f96951e269..9fb37c58e85 100644
--- a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
+++ b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
@@ -60,6 +60,14 @@ extern "C" void LLVMInitializePowerPCDisassembler() {
createPPCLEDisassembler);
}
+static DecodeStatus DecodePCRel24BranchTarget(MCInst &Inst, unsigned Imm,
+ uint64_t Addr,
+ const void *Decoder) {
+ int32_t Offset = SignExtend32<24>(Imm);
+ Inst.addOperand(MCOperand::createImm(Offset));
+ return MCDisassembler::Success;
+}
+
// FIXME: These can be generated by TableGen from the existing register
// encoding values!
diff --git a/llvm/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp b/llvm/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
index f4fcf58cedc..49e73891bc3 100644
--- a/llvm/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
+++ b/llvm/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
@@ -381,8 +381,11 @@ void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
// Branches can take an immediate operand. This is used by the branch
// selection pass to print .+8, an eight byte displacement from the PC.
- O << ".+";
- printAbsBranchOperand(MI, OpNo, O);
+ O << ".";
+ int32_t Imm = MI->getOperand(OpNo).getImm() << 2;
+ if (Imm >= 0)
+ O << "+";
+ O << Imm;
}
void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 7672f8da0fc..e54292aee28 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -736,7 +736,9 @@ def abscondbrtarget : Operand<OtherVT> {
def calltarget : Operand<iPTR> {
let PrintMethod = "printBranchOperand";
let EncoderMethod = "getDirectBrEncoding";
+ let DecoderMethod = "DecodePCRel24BranchTarget";
let ParserMatchClass = PPCDirectBrAsmOperand;
+ let OperandType = "OPERAND_PCREL";
}
def abscalltarget : Operand<iPTR> {
let PrintMethod = "printAbsBranchOperand";
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