summaryrefslogtreecommitdiffstats
path: root/llvm/lib
diff options
context:
space:
mode:
authorRafael Espindola <rafael.espindola@gmail.com>2006-07-18 17:00:30 +0000
committerRafael Espindola <rafael.espindola@gmail.com>2006-07-18 17:00:30 +0000
commitbf3a17cd32c7e5820fc421e6f88926512c1c0409 (patch)
tree33b6473ae7afa5e23fa56c319c6d35da851616e9 /llvm/lib
parentb00b6c2e865d18e973417cf5736f5beec82bd952 (diff)
downloadbcm5719-llvm-bf3a17cd32c7e5820fc421e6f88926512c1c0409.tar.gz
bcm5719-llvm-bf3a17cd32c7e5820fc421e6f88926512c1c0409.zip
initial prologue and epilogue implementation. Need to define add and sub before finishing it :-)
llvm-svn: 29175
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/ARM/ARMInstrInfo.td4
-rw-r--r--llvm/lib/Target/ARM/ARMRegisterInfo.cpp20
2 files changed, 23 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index 15a57c5a83d..4cf5acce849 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -53,7 +53,9 @@ def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
"!ADJCALLSTACKDOWN $amt",
[(callseq_start imm:$amt)]>;
-def bxr: InstARM<(ops IntRegs:$dst), "bx $dst", [(brind IntRegs:$dst)]>;
+let isReturn = 1 in {
+ def bx: InstARM<(ops IntRegs:$dst), "bx $dst", [(brind IntRegs:$dst)]>;
+}
def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", [(ARMcall tglobaladdr:$func)]>;
diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
index e7e1690596f..8daf0657948 100644
--- a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -116,10 +116,30 @@ void ARMRegisterInfo::
processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
+ MachineBasicBlock &MBB = MF.front();
+ MachineFrameInfo *MFI = MF.getFrameInfo();
+ int NumBytes = (int) MFI->getStackSize();
+
+ //hack
+ assert(NumBytes == 0);
+
+ //add a sp = sp - 4
+ BuildMI(MBB, MBB.begin(), ARM::str, 1, ARM::R14).addReg(ARM::R13);
}
void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
+ MachineBasicBlock::iterator MBBI = prior(MBB.end());
+ assert(MBBI->getOpcode() == ARM::bx &&
+ "Can only insert epilog into returning blocks");
+
+ MachineFrameInfo *MFI = MF.getFrameInfo();
+ int NumBytes = (int) MFI->getStackSize();
+ //hack
+ assert(NumBytes == 0);
+
+ BuildMI(MBB, MBBI, ARM::ldr, 2, ARM::R14).addImm(0).addReg(ARM::R13);
+ //add a sp = sp + 4
}
unsigned ARMRegisterInfo::getRARegister() const {
OpenPOWER on IntegriCloud