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authorEvan Cheng <evan.cheng@apple.com>2009-07-11 06:37:27 +0000
committerEvan Cheng <evan.cheng@apple.com>2009-07-11 06:37:27 +0000
commitbf041366c4e57cd0e2c81a16223f7c3a55830630 (patch)
tree55d507fde6e0a0711f8e5a811689002f8d86417e /llvm/lib
parentdcfdce9067178c396f5d3e70385f407343753f4b (diff)
downloadbcm5719-llvm-bf041366c4e57cd0e2c81a16223f7c3a55830630.tar.gz
bcm5719-llvm-bf041366c4e57cd0e2c81a16223f7c3a55830630.zip
80 col violation.
llvm-svn: 75358
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index f7e634a48cc..d7ba73c3e4b 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -588,8 +588,8 @@ ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
}
if (DestRC == ARM::GPRRegisterClass)
- AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::MOVr)), DestReg)
- .addReg(SrcReg)));
+ AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::MOVr)),
+ DestReg).addReg(SrcReg)));
else if (DestRC == ARM::SPRRegisterClass)
AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::FCPYS)), DestReg)
.addReg(SrcReg));
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